| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-04-02 | [RISCV] Slightly simplify RVVArgDispatcher::constructArgInfos. NFC (#87308) | Craig Topper | 1 | -4/+2 |
| 2024-04-02 | [RISCV][NFC] Delete some unused pseudo multiclasses (#87401) | Michael Maitland | 1 | -26/+0 |
| 2024-04-02 | [RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). (#87283) | Craig Topper | 1 | -1/+10 |
| 2024-04-02 | [RISCV][GISEL] Legalize G_BITCAST for scalable vectors (#85970) | Michael Maitland | 1 | -0/+6 |
| 2024-04-02 | [RISCV] Fix and refactor Zvk sched classes (#86519) | Michael Maitland | 2 | -41/+22 |
| 2024-04-02 | [RISCV][TTI] Scale the cost of trunc/fptrunc/fpext with LMUL (#87101) | Shih-Po Hung | 1 | -3/+22 |
| 2024-04-02 | [RISCV][TTI] Scale the cost of intrinsic umin/umax/smin/smax with LMUL (#87245) | Shih-Po Hung | 1 | -2/+20 |
| 2024-04-01 | [RISCV] ReadStoreData is read later in the pipeline for SiFive7 (#86454) | Michael Maitland | 1 | -1/+1 |
| 2024-04-01 | Recommit "[RISCV] Refine cost on Min/Max reduction (#79402)" (#86480) | Shih-Po Hung | 1 | -7/+36 |
| 2024-03-30 | [RISCV] RISCV vector calling convention (2/2) (#79096) | Brandon Wu | 3 | -71/+222 |
| 2024-03-29 | [RISCV] Move VPseudoBinaryNoMask multiclass to RISCVInstrInfoZvk.td and renam... | Craig Topper | 2 | -15/+15 |
| 2024-03-29 | [RISCV] Add missing RISCVMaskedPseudo for TIED pseudos (#86787) | Luke Lau | 1 | -2/+4 |
| 2024-03-29 | [RISCV] Combine (or disjoint ext, ext) -> vwadd (#86929) | Luke Lau | 1 | -6/+20 |
| 2024-03-28 | [RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001) | Philip Reames | 1 | -25/+25 |
| 2024-03-29 | [RISCV] Combine ({s,u}{div,rem} (zext, zext)) -> (zext ({s,u}{div,rem} (zext,... | Luke Lau | 1 | -2/+12 |
| 2024-03-28 | [RISCV] Add add_like PatFrags to reduce number of required patterns [nfc] (#8... | Philip Reames | 2 | -9/+7 |
| 2024-03-28 | [RISCV] Add validation of SPIMM for cm.push/pop. (#84989) | Craig Topper | 3 | -3/+9 |
| 2024-03-28 | [RISCV][GlobalISel] Fix legalizing ‘llvm.va_copy’ intrinsic (#86863) | bvlgah | 1 | -1/+1 |
| 2024-03-27 | [RISCV] Remove Unnecessary Semicolon. NFC (#86911) | hchandel | 1 | -1/+1 |
| 2024-03-27 | [RISCV] Model vd as a src for some Zvk* instructions in MC layer. (#86710) | Craig Topper | 2 | -21/+39 |
| 2024-03-27 | [Target][RISCV] Add HwMode support to subregister index size/offset. (#86368) | Craig Topper | 1 | -3/+8 |
| 2024-03-27 | [RISCV] RISCV vector calling convention (1/2) (#77560) | Brandon Wu | 4 | -28/+98 |
| 2024-03-26 | Recommit "[RISCV][TTI] Scale the cost of the sext/zext with LMUL (#86617)" | ShihPo Hung | 1 | -5/+15 |
| 2024-03-27 | [RISCV] Add areInlineCompatible for riscv target (#86639) | Jianjian Guan | 2 | -0/+17 |
| 2024-03-27 | [RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83... | Yeting Kuo | 1 | -3/+47 |
| 2024-03-26 | Revert "[RISCV][TTI] Scale the cost of the sext/zext with LMUL (#86617)" | ShihPo Hung | 1 | -15/+5 |
| 2024-03-26 | [RISCV] Align stack size down to a multiple of 16 before using cm.push/pop. (... | Craig Topper | 1 | -4/+8 |
| 2024-03-26 | [RISCV] Add register overlap checks to the assembler for some Zvk* instructio... | Craig Topper | 2 | -4/+10 |
| 2024-03-26 | [RISCV] Preserve MMO when expanding PseudoRV32ZdinxSD/PseudoRV32ZdinxLD. (#85... | Craig Topper | 1 | -7/+28 |
| 2024-03-27 | [RISCV][TTI] Scale the cost of the sext/zext with LMUL (#86617) | Shih-Po Hung | 1 | -5/+15 |
| 2024-03-26 | [RISCV][GISEL] Legalize, regbankselect, and instruction-select G_VSCALE (#85967) | Michael Maitland | 3 | -0/+57 |
| 2024-03-26 | [RISCV] Check that the stack adjust immediate for cm.push/pop* has the correc... | Craig Topper | 6 | -36/+71 |
| 2024-03-26 | [RISCV] Split compound if statement to fix a crash. | Craig Topper | 1 | -1/+4 |
| 2024-03-26 | [RISCV] Remove unneeded VAESKF_MV_I tablegen class. NFC | Craig Topper | 1 | -11/+3 |
| 2024-03-26 | [RISCV] Remove unnecessary overrides of a defaulted template argument. NFC | Craig Topper | 1 | -4/+4 |
| 2024-03-26 | [RISCV] Combine (mul (zext, zext)) -> (zext (mul (zext, zext))) (#86465) | Luke Lau | 1 | -0/+4 |
| 2024-03-25 | [RISCV][TTI] Fix missing return in the end of function | ShihPo Hung | 1 | -0/+1 |
| 2024-03-26 | [RISCV][TTI] Refactor getCastInstrCost to exit early (#86619) | Shih-Po Hung | 1 | -68/+65 |
| 2024-03-25 | [RISCV] Enable sub(max, min) lowering for ABDS and ABDU (#86592) | Philip Reames | 1 | -0/+20 |
| 2024-03-25 | [RISCV] Rename Binary->Ternary and Unary->Binary for some cases in RISCVInstr... | Craig Topper | 1 | -14/+14 |
| 2024-03-25 | [RISCV] Use inheritance instead of instantiating multiclasses inside another ... | Craig Topper | 1 | -4/+2 |
| 2024-03-25 | [RISCV] Remove ', vm' from comment for instruction that doesn't have mask. NFC | Craig Topper | 1 | -1/+1 |
| 2024-03-25 | [RISCV] Rename $merge to $rd in Zvk* pseudoinstructions and patterns. | Craig Topper | 1 | -10/+10 |
| 2024-03-25 | [RISCV] Remove more unneeded template parameters from RISCVInstrInfoZvk.td. NFC | Craig Topper | 1 | -6/+6 |
| 2024-03-25 | [RISCV] Remove unused Constraint template parameter from RISCVInstrInfoZvk.td... | Craig Topper | 1 | -34/+25 |
| 2024-03-25 | [RISCV] Remove unused tablegen class. NFC | Craig Topper | 1 | -16/+0 |
| 2024-03-25 | [RISCV] Remove unused forceMergeOpRead from SchedTernary class. NFC | Craig Topper | 1 | -4/+2 |
| 2024-03-25 | [RISCV] Fix indentation and 80 columns in RISCVInstrInfoZvk.td. NFC | Craig Topper | 1 | -28/+33 |
| 2024-03-25 | Revert "[RISCV][GISEL] Legalize G_VSCALE" | Michael Maitland | 3 | -57/+0 |
| 2024-03-25 | [RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuara... | Craig Topper | 2 | -0/+23 |
