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path: root/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
AgeCommit message (Expand)AuthorFilesLines
2023-08-14[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operandsPhilip Reames1-0/+46
2023-08-03[RISCV] Add bf16 to isFPImmLegal.Craig Topper1-0/+4
2023-08-02[RISCV] Copy memoperands in some of the post isel peepholes.Craig Topper1-4/+12
2023-07-31[RISCV] Use x0 in vsetvli when avl is equal to vlmax.Jianjian GUAN1-0/+6
2023-07-26[RISCV] Add patterns for vnsrl.vx where shift amount is truncatedLuke Lau1-4/+20
2023-07-21[RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]Luke Lau1-2/+3
2023-07-21[RISCV] Add patterns for vnsr[a,l].wx where shift amount has different type t...Luke Lau1-0/+10
2023-07-19Fix MSVC "'GetVMSetForLMul': not all control paths return a value" warning. NFC.Simon Pilgrim1-0/+1
2023-07-19[RISCV] Fold ops into vmv.v.v as vmerge with all-ones maskLuke Lau1-36/+96
2023-07-19[RISCV] Fold vmerge into its ops with smaller VL if knownLuke Lau1-4/+18
2023-07-18[RISCV] Minor style cleanups in post ISEL combinesPhilip Reames1-11/+5
2023-07-16[RISCV] Implement prefetch locality by NTLHPiyou Chen1-0/+30
2023-07-15[RISCV] Use isScalarInteger instead of isInteger. NFCCraig Topper1-1/+1
2023-07-13[RISCV] Common remaining operand logic in performCombineVMergeAndVOps [nfc]Philip Reames1-32/+16
2023-07-13[RISCV] Reason explicitly about mask and rounding mode in performCombineVMerg...Philip Reames1-6/+21
2023-07-13[RISCV] Common post-mask operand construction in performCombineVMergeAndVOps ...Philip Reames1-8/+11
2023-07-13[RISCV] Tail common repeated code in performCombineVMergeAndVOps [nfc]Philip Reames1-3/+3
2023-07-13[RISCV] Factor out a dupiicate bit of repeated code in performCombineVMergeAn...Philip Reames1-5/+6
2023-07-13[RISCV] Simplify glue handling logic in performCombineVMergeAndVOps [nfc]Philip Reames1-4/+7
2023-07-13[RISCV] Don't fold vmerge into ops if fp exception can be raisedLuke Lau1-9/+12
2023-07-13[RISCV][POC] Model frm control for vfaddeopXD1-2/+16
2023-07-12[RISCV] Remove legacy TA/TU pseudo distinction of vmerge and carry-in arithme...Philip Reames1-35/+22
2023-07-11[RISCV] Cleanup dead complexity in RISCVMaskedPseudo after TA/TU merge refact...Philip Reames1-57/+15
2023-07-11[RISCV] Don't fold RISCVISD::VMV_V_X_VL series node and scalar load to vector...Zi Xuan Wu (Zeson)1-1/+3
2023-07-05[RISCV] Remove legacy TA/TU pseudo distinction for load instructionsPhilip Reames1-60/+49
2023-07-04[RISCV][NFC] Fix doc comment for RISCVDAGToDAGISel::selectSETCCAlex Bradbury1-2/+2
2023-06-29[RISCV] Remove legacy TA/TU pseudo distinction for unary instructionsPhilip Reames1-3/+7
2023-06-29[RISCV] Remove unused variables in RISCVISelDAGToDAG.cpp (NFC)Jie Fu1-3/+0
2023-06-29[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL nodeYunze Zhu1-5/+4
2023-06-27[RISCV] Fix a typo in a commentPhilip Reames1-1/+1
2023-06-16[RISCV] Fix a latent miscompile in doPeepholeMaskedRVVPhilip Reames1-7/+6
2023-06-16[RISCV] Refactor vecPolicyOp skip logic in doPeepholeMaskedRVV. NFCLuke Lau1-4/+6
2023-06-16[RISCV] Reuse RISCVDAGToDAGISel member TTI in doPeepholeMaskedRVV. NFCLuke Lau1-3/+2
2023-06-16[RISCV] Treat __riscv_vsetvl_*(-1) as vlmax.Craig Topper1-1/+1
2023-06-16[RISCV][NFC] Simplify code.Jianjian GUAN1-8/+4
2023-06-14[RISCV] Remove dead code from doPeepholeMaskedRVV [nfc]Philip Reames1-8/+5
2023-06-14[RISCV] Canonicalize towards vid w/passthrough representationPhilip Reames1-7/+14
2023-06-13[RISCV] Minor style changes to performCombineVMergeAndVOps [nfc]Philip Reames1-14/+19
2023-06-13[RISCV] Canonicalize towards vmerge w/passthrough representationPhilip Reames1-4/+15
2023-06-12[RISCV] Fix an unused variable warningKazu Hirata1-1/+0
2023-06-12[RISCV] Begin removing hasDummyMask.Craig Topper1-6/+3
2023-06-12[RISCV] Use tail undisturbed vmv.v.v instead of vadd.vi with 0 for vp.merge w...Craig Topper1-30/+17
2023-06-06[RISCV] Fix UBSan failure on signed integer overflow.Craig Topper1-1/+1
2023-06-06Revert "Revert "[RISCV] Add special case to selectImm for constants that can ...Florian Mayer1-0/+23
2023-06-06Revert "[RISCV] Add special case to selectImm for constants that can be creat...Florian Mayer1-23/+0
2023-06-06[RISCV] Use const reference when looping over RISCVMatInt::InstSeq. NFCCraig Topper1-1/+1
2023-06-06[RISCV] Add special case to selectImm for constants that can be created with ...Craig Topper1-0/+23
2023-06-06[RISCV] Remove uses of RISCVII::hasMergeOp from RISCVDAGToDAGISel.cppCraig Topper1-16/+21
2023-06-06[RISCV] Handle "o" inline asm memory constraintwangpc1-1/+3
2023-05-29[RISCV] Teach performCombineVMergeAndVOps to handle instructions FMA instruct...Craig Topper1-13/+29
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