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path: root/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
AgeCommit message (Expand)AuthorFilesLines
2024-04-04[RISCV] Add patterns for fixed vector vwsll (#87316)Luke Lau1-15/+15
2024-03-20[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and G...Craig Topper1-0/+37
2024-02-26[RISCV] Fix insert_subvector with fixed vector type creating invalid node (#8...Luke Lau1-3/+5
2024-02-23[RISCV] Add asserts for insert/extract_subvector invariants. NFCLuke Lau1-2/+6
2024-02-20[RISCV] Add a query for exact VLEN to RISCVSubtarget [nfc]Philip Reames1-3/+2
2024-02-06[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variab...Yeting Kuo1-6/+5
2024-01-28[Target] Use getConstantOperand (NFC)Kazu Hirata1-2/+1
2024-01-26[RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (#79407)Brandon Wu1-0/+64
2024-01-24[RISCV] Update performCombineVMergeAndVOps comments. NFC (#78472)Luke Lau1-17/+25
2024-01-17Revert "[RISCV] Remove dead early exit in performCombineVMergeAndVOps. NFC"Luke Lau1-0/+3
2024-01-17[RISCV] Remove dead early exit in performCombineVMergeAndVOps. NFCLuke Lau1-3/+0
2024-01-08[RISCV][NFC] Fix gcc -Wparentheses warning in RISCVISelDAGToDAG.cppLiao Chunyu1-2/+2
2024-01-04[RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (#76922)Craig Topper1-6/+4
2024-01-02[llvm][NFC] Use SDValue::getConstantOperandVal(i) where possible (#76708)Alex Bradbury1-3/+3
2023-12-19[RISCV] Update implies for subtarget feature. (#75824)Yeting Kuo1-2/+1
2023-12-02[llvm] Stop including optional (NFC)Kazu Hirata1-1/+0
2023-11-27[RISCV] Partially move doPeepholeMaskedRVV into RISCVFoldMasks (#72441)Philip Reames1-2/+4
2023-11-22[llvm][TypeSize] Fix addition/subtraction in TypeSize. (#72979)Sander de Smalen1-2/+2
2023-11-13[RISCV] Fix lowering of negative zero with Zdinx 32-bit (#71869)Nemanja Ivanovic1-5/+10
2023-11-10[RISCV] Peek through zext in selectShiftMask.Craig Topper1-1/+6
2023-11-09[RISCV] Use Align(8) for the stack temporary created for SPLAT_VECTOR_SPLIT_I...Craig Topper1-1/+1
2023-11-09[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#7...Wang Pengcheng1-6/+4
2023-11-07[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)Yeting Kuo1-0/+5
2023-11-01[RISCV] Add experimental support for making i32 a legal type on RV64 in Selec...Craig Topper1-3/+9
2023-10-31[RISCV] Use FLI + FNEG to materialize some negative FP constants (#70825)Min-Yih Hsu1-5/+17
2023-10-30[RISCV] Begin moving post-isel vector peepholes to a MF pass (#70342)Luke Lau1-36/+0
2023-10-30[RISCV][NFC] Move getRVVMCOpcode to RISCVInstrInfo (#70637)Wang Pengcheng1-16/+5
2023-10-25[RISCV] Add an experimental pseudoinstruction to represent a rematerializable...Craig Topper1-0/+13
2023-10-23[RISCV] Only check for scalar VT at depth 0 in hasAllNBitUsers.Craig Topper1-1/+1
2023-10-22[RISCV] Disable hasAllNBitUsers for vector types.Craig Topper1-0/+5
2023-10-20[RISCV] Match prefetch address with offset (#66072)Wang Pengcheng1-1/+73
2023-10-18Add RV64 constraint to SRLIW (#69416)Shao-Ce SUN1-5/+5
2023-10-03[RISCV] Move vector pseudo hasAllNBitUsers switch into RISCVInstrInfo. NFC (#...Luke Lau1-114/+3
2023-10-02[RISCV] Generalize the (ADD (SLLI X, 32), X) special case in constant materia...Craig Topper1-18/+12
2023-10-01[RISCV] Add missing hunk to #67889 to fix test failuresAlex Bradbury1-1/+7
2023-09-27[RISCV] Fix -Wsign-compare warning. NFCCraig Topper1-1/+1
2023-09-27[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)Luke Lau1-0/+144
2023-09-27Revert "[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)"Philip Reames1-25/+1
2023-09-27[RISCV] Handle .vx pseudos in hasAllNBitUsers (#67419)Luke Lau1-1/+25
2023-09-26[RISCV] Explicitly create IMPLICIT_DEF instead of UNDEF for vectors i… (#67...Craig Topper1-2/+3
2023-09-22[RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL foldPhilip Reames1-0/+5
2023-09-22[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)Luke Lau1-0/+6
2023-09-14[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#6...Arthur Eubanks1-1/+1
2023-09-13reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66264)Nick Desaulniers1-4/+5
2023-09-13Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)"Reid Kleckner1-5/+4
2023-09-13[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)Nick Desaulniers1-4/+5
2023-08-31[RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some cons...Craig Topper1-3/+7
2023-08-30[RISCV] Form vmv.s.f/x from single element splats via DAG combinePhilip Reames1-1/+2
2023-08-29[RISCV] Refactor selectVSplat. NFCILuke Lau1-39/+33
2023-08-22[RISCV] Don't relax policy to ta when vmerge's VL shrinks during foldingLuke Lau1-1/+12
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