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2024-04-19[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)Craig Topper1-4/+4
Planning to declare all extensions in tablegen so we can generate the tables for RISCVISAInfo.cpp. This requires making "e" consistent with other extensions.
2024-04-18[RISCV] Remove unused HasStdExtZama16b Predicate. NFCCraig Topper1-3/+0
2024-04-17[RISCV] Remove unused Predicates for I and E extensions. NFCCraig Topper1-5/+1
2024-04-17[RISCV] Support Zama16b1p0 (#88474)Jesse Huang1-0/+7
This patch adds the support for Zama16b version 1.0, which has been added to RVA23U64 optional extensions recently
2024-04-16[RISCV] Re-separate unaligned scalar and vector memory features in the ↵Craig Topper1-4/+9
backend. (#88954) This is largely a revert of commit e81796671890b59c110f8e41adc7ca26f8484d20. As #88029 shows, there exists hardware that only supports unaligned scalar. I'm leaving how this gets exposed to the clang interface to a future patch.
2024-04-16[RISCV] Generate more W instructonsPengcheng Wang1-3/+3
We rename `TuneNoStripWSuffix` to `TunePreferWInst`. If all the users of an instruction just use the low 32 bits, we can convert it to its W variant. A quick test on Coremark (`-O3 -march=rv64gc`): | | W instructions | code size(.text) | |--------|----------------|------------------| | before | 302 | 12257 | | after | 343 | 12265 | | | +13.58% | +0.065% | Reviewers: asb, dtcxzyw, preames, lukel97, michaelmaitland, topperc Reviewed By: topperc, dtcxzyw Pull Request: https://github.com/llvm/llvm-project/pull/87237
2024-04-08[RISCV] Zimop/Zcmop are ratifiedPengcheng Wang1-2/+2
Remove them from experimental. See also: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc Reviewers: kito-cheng Reviewed By: kito-cheng Pull Request: https://github.com/llvm/llvm-project/pull/87966
2024-03-25[RISCV] Add a tune feature to disable stripping W suffix (#86255)Wang Pengcheng1-0/+4
We have a hidden option to disable it, but I'd like to make it a tune feature. For some implementations, instructions with W suffix would be less costly as they only perform on 32 bits data. Though we may lose some chances to compress.
2024-03-13[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease ↵Craig Topper1-0/+24
instructions. (#83896) These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension name being used. This restores them with new extension names that match SiFive's downstream compiler. The extension name has been used internally for some time. It uses XSiFive instead of XSf like the newer extensions. `cease` did not have an internal extension name so its using the `XSf` convention. The spec for the instructions is here https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf though the extension name is not listed. Column width in the extension printing had to be changed to accommodate a longer extension name.
2024-03-05[RISCV] Remove note of Sscofpmf and add a newline after ↵Wang Pengcheng1-0/+1
FeatureStdExtSscofpmf (#83958) To address comments after committing #83831.
2024-03-05[RISCV] Add support of Sscofpmf (#83831)Wang Pengcheng1-0/+3
This is used in profile, but somehow we missed it.
2024-02-28[RISCV] Remove experimental from Zacas. (#83195)Craig Topper1-1/+1
Document that we don't use the double compare and swap instructions due to ABI concerns.
2024-02-15[RISCV] Use RISCVSubtarget::hasStdExtCOrZcd() in HasStdExtCOrZcd tablgen ↵Craig Topper1-1/+1
Predicate. NFC
2024-02-10[RISCV] Add Zicfiss support to the shadow call stack implementation. (#68075)Yeting Kuo1-0/+5
This patch enable hardware shadow stack with `Zicifss` and `mno-forced-sw-shadow-stack`. New feature forced-sw-shadow-stack disables hardware shadow stack even when `Zicfiss` enabled.
2024-02-06[RISCV] Add Ssqosid support to -march. (#80747)Craig Topper1-0/+4
2024-02-05[RISCV] Fix description of Ssstrict to have a closing parenthesis.Craig Topper1-1/+1
2024-02-05[RISCV] Add support for RISC-V Pointer Masking (#79929)Michael Maitland1-0/+34
This patch implements the v0.8.1 specification. This patch reports version 0.8 in llvm since `RISCVISAInfo::ExtensionVersion` only has a `Major` and `Minor` version number. This patch includes includes support of the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make up RISC-V pointer masking. All of these extensions require emitting attribute containing correct `march` string. `Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a 2-bit WARL field (PMM). The extension does not specify how PMM is set, and therefore this patch does not need to address this. One example of how it *could* be set is using the Zicsr instructions to update the PMM bits of the described registers. The full specification can be found at https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
2024-02-02[RISCV] Rename some SubtargetFeature names to remove an extra 's'. NFCCraig Topper1-3/+3
I wrote FeaturesStdExt instead of FeatureStdExt in a previous patch.
2024-02-01[RISCV] Add -march support for many of the S extensions mentioned in the ↵Craig Topper1-0/+65
profile specification. (#79399) This is a good portion of the extensions mentioned in the RVA23 profile here https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc I don't believe these add any new CSRs. Sstc does add new CSRs, but we already added them without the extension name a while back. I tried to keep the descriptions in RISCVFeatures.td fairly short since the strings show up in `-print-supported-extensions`.
2024-02-01[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)Brendan Sweeney1-0/+7
This PR implements experimental support for the RISC-V Atomic Load-Acquire and Store-Release Extension (Zalasr). It has been approved to be pursued as a fast track extension (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698), but has not yet been approved by ARC or ratified. See https://github.com/mehnadnerd/riscv-zalasr for draft spec. --------- Co-authored-by: brs <turtwig@utexas.edu> Co-authored-by: Philip Reames <preames@rivosinc.com>
2024-01-31[RISCV][MC] Add MC layer support for the experimental zabha extension (#80005)Yingwei Zheng1-0/+7
This patch implements the zabha (Byte and Halfword Atomic Memory Operations) v1.0-rc1 extension. See also https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc.
2024-01-29[RISCV] Graduate Zicond to non-experimental (#79811)Alex Bradbury1-1/+1
The Zicond extension was ratified in the last few months, with no changes that affect the LLVM implementation. Although there's surely more tuning that could be done about when to select Zicond or not, there are no known correctness issues. Therefore, we should mark support as non-experimental.
2024-01-25[RISCV] Add Tune to DontSinkSplatOperands (#79199)Michael Maitland1-0/+7
A CPU may prefer to not sink splat operands, one reason being that it could require a S2V transfer buffer to move scalars into buffers.
2024-01-25[RISCV] Use TableGen-based macro fusion (#72224)Wang Pengcheng1-24/+0
We convert existed macro fusions to TableGen. Bacause `Fusion` depend on `Instruction` definitions which is defined below `RISCVFeatures.td`, so we recommend user to add fusion features when defining new processor.
2024-01-25[RISCV][MC] Add experimental support of Zaamo and ZalrscWang Pengcheng1-0/+18
`A` extension has been split into two parts: Zaamo (Atomic Memory Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also https://github.com/riscv/riscv-zaamo-zalrsc. This patch adds the MC support. Reviewers: dtcxzyw, topperc, kito-cheng Reviewed By: topperc Pull Request: https://github.com/llvm/llvm-project/pull/78970
2024-01-23[RISCV] Move FeatureStdExtH in RISCVFeatures.td. NFCCraig Topper1-8/+10
It was accidentally in the middle of the floating point extensions after the recent reordering.
2024-01-23[RISCV] Re-format RISCVFeatures.td so it doesn't look like ↵Craig Topper1-208/+215
AssemblerPredicate is an operand to Predicate. (#79076) AssemblerPredicate was almost always indented to the same column as the first operand to Predicate. But AssemblerPredicate is a separate base class so should have the same indentation as Predicate. For the string passed to AssemblePredicate, I aligned it to the other arguments on the previous if it fit in 80 columns. Otherwise I indented 4 spaces past the start of AssemblerPredicate. For some vendor extensions I put the 2 classes on new lines instead of the same line as the def. This gave more room for the strings and was more consistent with other formatting in that portion of the file.
2024-01-22[RISCV] Combine HasStdExtZfhOrZfhmin and HasStdExtZfhmin. NFC (#78826)Craig Topper1-13/+2
I kept the AssemblerPredicate and diagnostic from HasStdExtZfhOrZfhmin that mentions both extensions, but replaced all uses with HasStdExtZfhmin. Same for the Zhinxmin equivalent.
2024-01-22[RISCV] Arrange RISCVFeatures.td into sections of related extensions. NFC ↵Craig Topper1-274/+304
(#78790) Put I and Zi* together. Put F/D/Zf* together. Put A and Za* together, etc.
2024-01-19[RISCV] Add support for Smepmp 1.0 (#78489)Min-Yih Hsu1-0/+4
Smepmp is a supervisor extension that prevents privileged processes from accessing unprivileged program and data. Spec: https://github.com/riscv/riscv-tee/blob/main/Smepmp/Smepmp.pdf
2024-01-19[RISCV] Add support for new unprivileged extensions defined in profiles spec ↵Luke Lau1-0/+26
(#77458) This adds minimal support for 7 new unprivileged extensions that were defined as a part of the RISC-V Profiles specification here: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions * Ziccif: Main memory supports instruction fetch with atomicity requirement * Ziccrse: Main memory supports forward progress on LR/SC sequences * Ziccamoa: Main memory supports all atomics in A * Zicclsm: Main memory supports misaligned loads/stores * Za64rs: Reservation set size of 64 bytes * Za128rs: Reservation set size of 128 bytes * Zic64b: Cache block size isf 64 bytes As stated in the specification, these extensions don't add any new features but describe existing features. So this patch only adds parsing and subtarget features.
2024-01-16[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)Wang Pengcheng1-0/+7
This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401
2024-01-12[RISCV] Update descriptions for Zvk* shorthands. (#77961)Craig Topper1-12/+8
This makes them more consistent with other extensions so they appear move similar in the -print-supported-extensions output.
2024-01-11[RISCV] Simplify the description for ssaia and smaia. (#77870)Craig Topper1-7/+4
It feels more important to expand out Advanced Interrupt Architecture for users than to have a description that explains how one extension is different from the other.
2024-01-11[RISCV] Remove period from Zvbb extension description.Craig Topper1-2/+2
No other instruction extension has a period. There are also periods in 'ssaia' and 'smaia', but those descriptions need a different update.
2024-01-10[RISCV] Support isel for Zacas for XLen and i32. (#77666)Craig Topper1-0/+1
This adds new isel patterns for Zacas that take priority over the pseudoinstructions we use for the A extension. Support for 2x XLen types will come in a separate patch since they need to be done differently.
2024-01-08[RISCV] Add branch+c.mv macrofusion for sifive-p450. (#76169)Craig Topper1-0/+6
sifive-p450 supports a very restricted version of the short forward branch optimization from the sifive-7-series. For sifive-p450, a branch over a single c.mv can be macrofused as a conditional move operation. Due to encoding restrictions on c.mv, we can't conditionally move from X0. That would require c.li instead.
2023-12-30[RISCV] Add MC layer support for Zicfiss. (#66043)Yeting Kuo1-0/+9
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to support shadow stack for control flow integrity. This patch is based on version [0.3.1]. [0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
2023-12-28[RISCV] Remove XSfcie extension.Craig Topper1-7/+0
This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and 4c37d30e22ae655394c8b3a7e292c06d393b9b44. XSfcie is not an official SiFive extension name. It stands for SiFive Custom Instruction Extension, which is mentioned in the S76 manual, but then elsewhere in the manual says it is not supported for S76. LLVM had various instructions and CSRs listed as part of this extension, but as far as SiFive is concerned, none of them are part of it. There are no documented extension names for these instructions and CSRs either externally or internally. If these are important to LLVM users, I can facilitate creating extension names for them and have them documented. For now I'm removing everything. Unfortunately, these instructions and CSRs are in LLVM 17 so this is an incompatible change.
2023-12-28[RISCV][MC] Add support for experimental Zcmop extension (#76395)Wang Pengcheng1-0/+7
This implements experimental support for the Zcmop extension as specified here: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc. This change adds only MC support.
2023-12-26[RISCV][MC] Add support for experimental Zimop extension (#75182)Jivan Hakobyan1-0/+6
This implements experimental support for the Zimop extension as specified here: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc. This change adds only assembly support. --------- Co-authored-by: ln8-8 <lyut.nersisyan@gmail.com> Co-authored-by: ln8-8 <73429801+ln8-8@users.noreply.github.com>
2023-12-22[RISCV] Split TuneShiftedZExtFusion (#76032)Wang Pengcheng1-3/+13
We split `TuneShiftedZExtFusion` into three fusions to make them reusable and match the GCC implementation[1]. The zexth/zextw fusions can be reused by XiangShan[2] and other commercial processors, but shifted zero extension is not so common. `macro-fusions-veyron-v1.mir` is renamed so it's not relevant to specific processor. References: [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637303.html [2] https://xiangshan-doc.readthedocs.io/zh_CN/latest/frontend/decode
2023-12-22[RISCV] Rename TuneVeyronFusions to TuneVentanaVeyronwangpc1-6/+2
And fusion features are added to processor definition.
2023-12-19[RISCV] Remove Zfbfmin dependency from Zvfbfmin. (#75851)Craig Topper1-2/+2
Zvfbfmin does not have any scalar operands making this an unnecessary dependency. The spec was just updated to remove this. See https://github.com/riscv/riscv-bfloat16/commit/86d7a74f4b928e981f79f6d84a4592e6e9e4c0e9 This fixes a correctness issue where Xsfvfwmaccqqq was incorrectly depending on Zfbfmin. The SiFive CPUs that support Xsfvfwmaccqqq do not implement Zfbfmin, but do implement Zvfbfmin based on a previous understanding that it only requires Zve32f. I've added tests for this feature to raise the bar for adding dependencies to it in the future.
2023-12-18[RISCV] Remove experimental from Vector Crypto extensions (#74213)Eric Biggers1-16/+20
The RISC-V vector crypto extensions have been ratified. This patch updates the Clang and LLVM support for these extensions to be non-experimental, while leaving the C intrinsics as experimental since the C intrinsics are not yet standardized. Co-authored-by: Brandon Wu <brandon.wu@sifive.com>
2023-12-19[RISCV] Update implies for subtarget feature. (#75824)Yeting Kuo1-11/+11
PR #75576 and #75735 update some implies in llvm/lib/Support/RISCVISAInfo.cpp, but both of them miss the subtarget feature part. This patch still preserve predicate HasStdExtZfhOrZfhmin and HasStdExtZhinxOrZhinxmin, since they could make error message more readable. ( Users might not know that zfh implies zfhmin.)
2023-12-11[RISCV] Macro-fusion support for veyron-v1 CPU. (#70012)Mikhail Gudim1-3/+16
Support was added for the following fusions: auipc-addi, slli-srli, ld-add Some parts of the code became repetative, so small refactoring of existing lui-addi fusion was done.
2023-12-01[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)Philip Reames1-9/+4
When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they were separated into two parts under the theory that some processor might implement one, but not the other. At the moment, we don't have evidence of such a processor. The C/C++ level interface, and the clang driver command lines have settled on a single unaligned flag which indicates both scalar and vector support unaligned. Given that, let's remove the test matrix complexity for a set of configurations which don't appear useful. Given these are internal feature names, I don't think we need to provide any forward compatibility. Anyone disagree? Note: The immediate trigger for this patch was finding another case where the unaligned-vector-mem wasn't being properly serialized to IR from clang which resulted in problems reproducing assembly from clang's -emit-llvm feature. Instead of fixing this, I decided getting rid of the complexity was the better approach.
2023-11-16[RISCV] Simplify assembler error information for RVV instructions (#72469)Jianjian Guan1-4/+4
Since vector embedded extensions have dependence, we don't have to show several extensions in the error messages.
2023-11-16[RISCV][MC] MC layer support for xcvmem and xcvelw extensionsLiaoChunyu1-0/+15
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P. Several other extensions have been merged. Spec: https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D158824
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