| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-07-27 | [CSKY] Fix the btsti16 instruction missing in generic processor | Zi Xuan Wu (Zeson) | 1 | -1/+3 |
| 2022-02-08 | [CSKY] Add CK800 series ProcessorModel and complete related SubtargetFeatures | Zi Xuan Wu | 1 | -0/+523 |
| 2022-01-27 | [CSKY] Add floating operation support including float and double | Zi Xuan Wu | 1 | -0/+34 |
| 2021-11-08 | [CSKY] Add CSKY 16-bit instruction format and encoding | Zi Xuan Wu | 1 | -0/+12 |
| 2021-11-01 | [CSKY] First patch to construct codegen infra and generate first add instruction | Zi Xuan Wu | 1 | -0/+1 |
| 2021-10-20 | [CSKY] Complete to add basic integer instruction set | Zi Xuan Wu | 1 | -0/+74 |
| 2021-04-20 | [CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter | Zi Xuan Wu | 1 | -1/+14 |
| 2020-12-07 | [CSKY 2/n] Add basic tablegen infra for CSKY | Zi Xuan Wu | 1 | -0/+32 |
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index : rocket-tools/riscv-gnu-toolchain/llvm.git | |
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