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2024-02-23[AMDGPU] Simplify AMDGPUDisassembler::getInstruction by removing Res. (#82775)Jay Foad2-151/+119
2024-02-23[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)Ivan Kosarev10-89/+74
2024-02-23[AMDGPU] Fix encoding of VOP3P dpp on GFX11 and GFX12 (#82710)Stanislav Mekhanoshin2-0/+3
2024-02-22[AMDGPU][NFC] Refactor SIInsertWaitcnts zero waitcnt generation (#82575)vangthao952-15/+22
2024-02-22[AMDGPU] Remove DPP DecoderNamespaces. NFC. (#82491)Jay Foad6-400/+288
2024-02-22[AMDGPU] Clean up conversion of DPP instructions in AMDGPUDisassembler (#82480)Jay Foad1-74/+53
2024-02-22[AMDGPU] Split Dpp8FI and Dpp16FI operands (#82379)Jay Foad8-46/+43
2024-02-22[AMDGPU][GlobalISel] Add fdiv / sqrt to rsq combine (#78673)Nick Anderson2-1/+30
2024-02-21[AMDGPU] fixes mistake in #82018 (#82223)Nick Anderson1-1/+1
2024-02-21[AMDGPU][TableGen][NFC] Combine predicates without using classes. (#82346)Ivan Kosarev1-10/+4
2024-02-21Revert "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe5-64/+12
2024-02-21[AMDGPU] Fix linking error of SIISelLowering.cpp.o (NFC)Jie Fu1-2/+4
2024-02-21Implement convergence control in MIR using SelectionDAG (#71785)Sameer Sahasrabuddhe5-12/+62
2024-02-20[AMDGPU] Fix v_dot2_f16_f16/v_dot2_bf16_bf16 operands (#82423)Stanislav Mekhanoshin3-18/+12
2024-02-20AMDGPU: Use HasFP8ConversionInsts appropriately, NFC (#82433)Changpeng Fang3-6/+9
2024-02-20[AMDGPU] Add v2bf16 for opsel immediate folding (#82435)Stanislav Mekhanoshin1-0/+2
2024-02-20[AMDGPU] Fix operand types for `V_DOT2_F32_BF16` (#82044)Shilei Tian2-2/+2
2024-02-20[AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (#82233)Jay Foad4-61/+36
2024-02-20[AMDGPU] Try decoding instructions longest first. NFCI. (#82014)Jay Foad2-42/+45
2024-02-20[AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (#82245)Ivan Kosarev5-27/+43
2024-02-19[AMDGPU] Fix bf16 inv2pi inline constant hadling (#82283)Stanislav Mekhanoshin1-7/+18
2024-02-19[AMDGPU] Fix decoder for BF16 inline constants (#82276)Stanislav Mekhanoshin4-110/+176
2024-02-19[AMDGPU][MC][True16] Support V_RCP/SQRT/RSQ/LOG/EXP_F16. (#81131)Ivan Kosarev1-0/+5
2024-02-18[AMDGPU] fixes duplicate expressions in if stmnts in SIISelLowering.cpp (#82018)Nick Anderson1-2/+2
2024-02-17[AMDGPU] Set predicates more consistently for BUF instructions (#81865)Jay Foad2-232/+217
2024-02-17[AMDGPU] Use HasClamp instead of HasIntClamp in VOP3_Pseudo. NFC. (#82020)Stanislav Mekhanoshin1-1/+1
2024-02-16[AMDGPU] Use `bf16` instead of `i16` for bfloat (#80908)Shilei Tian11-10/+311
2024-02-16[AMDGPU] Consolidate SGPRSpill and VGPRSpill into single Spill bit (#81901)Corbin Robeck5-24/+41
2024-02-16[AMDGPU] Rewrite `getVOPSrc0ForVT` with `!cond` (#81956)Shilei Tian1-31/+19
2024-02-16[AMDGPU] Fix Ins64 clamp in the VOPProfile. NFC. (#81925)Stanislav Mekhanoshin1-1/+1
2024-02-16[AMDGPU] Rewrite `getVregSrcForVT` with `!cond` (#81954)Shilei Tian1-9/+8
2024-02-16[AMDGPU] Set DecoderNamespace consistently for GFX10+ MIMG instructions (#81881)Jay Foad1-23/+23
2024-02-16[AMDGPU] Reimplement V_READFIRSTLANE_B32 as a normal VOP1 Pseudo. NFCI. (#81877)Jay Foad1-31/+24
2024-02-15[AMDGPU] Rewrite `getVOP3DPPSrcForVT` with `!cond` (#81889)Shilei Tian1-7/+9
2024-02-15[AMDGPU] Make maximum hard clause size a subtarget feature (#81287)Krzysztof Drewniak3-11/+34
2024-02-15[AMDGPU] Clean up functions for checking inline literals (#81282)Shilei Tian6-39/+12
2024-02-15[AMDGPU] Use consistent DecoderNamespace for wave64 instructions. NFC. (#81863)Jay Foad2-4/+4
2024-02-15[AArch64][GlobalISel] Refactor Combine G_CONCAT_VECTOR (#80866)chuongg31-2/+0
2024-02-15[AMDGPU] Add 256-bit vdst and 96-bit src to profile switches. NFC. (#81801)Stanislav Mekhanoshin2-39/+28
2024-02-14[AMDGPU] Refactor export instruction definitions. NFC. (#81738)Jay Foad1-68/+58
2024-02-14[AMDGPU] Replace '.' with '-' in generic target names (#81718)Pierre van Houtryve1-2/+2
2024-02-14[AMDGPU] Make use of defvar in DSDIR definitions. NFC.Jay Foad1-4/+4
2024-02-13[LLVM] Add `__builtin_readsteadycounter` intrinsic and builtin for realtime c...Joseph Huber4-0/+21
2024-02-13[AMDGPU][NFC] Get rid of some operand decoders defined using macros. (#81482)Ivan Kosarev2-138/+111
2024-02-13[AMDGPU] Use LLT::isPointerOrPointerVector in legalizer (#81582)Jay Foad1-5/+2
2024-02-13[LLT] Add and use isPointerVector and isPointerOrPointerVector. NFC. (#81283)Jay Foad1-3/+2
2024-02-13[AMDGPU][SIMemoryLegalizer] Fix order of GL0/1_INV on GFX10/11 (#81450)Pierre van Houtryve1-1/+4
2024-02-13[AMDGPU][GlobalIsel] Introduce isRegisterClassType to check for legal types, ...sstipanovic1-50/+85
2024-02-12[AMDGPU] Enable kernel arg preloading with gfx90a (#81180)Austin Kerbow6-17/+21
2024-02-12AMDGPU/NFC: Remove some bits from TSFlags (#81525)Konstantin Zhuravlyov9-35/+26
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