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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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2024-02-22[AArch64] Switch to soft promoting half types. (#80576)Harald van Dijk1-0/+2
2024-01-31[AArch64][SVE2] Generate urshr rounding shift rights (#78374)Usman Nadeem1-0/+1
2024-01-31[SME] Stop RA from coalescing COPY instructions that transcend beyond smstart...Sander de Smalen1-1/+3
2024-01-22Arm64EC entry/exit thunks, consolidated. (#79067)Eli Friedman1-0/+5
2024-01-20[AArch64][SME2] Preserve ZT0 state around function calls (#78321)Kerry McLaughlin1-0/+2
2024-01-18[AArch64][SME] Conditionally do smstart/smstop (#77113)Matthew Devereau1-4/+4
2024-01-15[AArch64][GlobalISel] Combine vecreduce(ext) to {U/S}ADDLV (#75832)chuongg31-0/+1
2023-12-05[CGP][AArch64] Rebase the common base offset for better ISelzhongyunde 004434071-0/+3
2023-12-02[AArch64] Stack probing for dynamic allocas in SelectionDAG (#66525)Momchil Velikov1-3/+10
2023-12-01[AArch64][SME] Remove implicit-def's on smstart (#69012)Jon Roelofs1-0/+3
2023-12-01[AArch64][SME2] Add SME2 builtins for zero { zt0 } (#72274)Matthew Devereau1-2/+2
2023-12-01[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#72849)Matt Devereau1-0/+2
2023-11-30[AArch64] Stack probing for function prologues (#66524)Momchil Velikov1-0/+10
2023-11-30[LLVM][SVE] Honour calling convention when using SVE for fixed length vectors...Paul Walker1-0/+12
2023-11-21[AArch64] Add SVE2.1 intrinsics for indexed quadword gather loads and scatter...Momchil Velikov1-0/+2
2023-11-21[AArch64][SVE2.1] Add intrinsics for quadword loads/stores with unscaled offs...Momchil Velikov1-0/+2
2023-11-20[AArch64][SME] Remove immediate argument restriction for svldr and svstr (#68...Sam Tebbs1-0/+4
2023-11-16Revert "[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#71795)"Matt Devereau1-2/+0
2023-11-14[CodeGen][AArch64] Set min jump table entries to 13 for AArch64 targets (#71166)David Sherwood1-0/+2
2023-11-14[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#71795)Matthew Devereau1-0/+2
2023-10-31[AArch64] Add intrinsic to count trailing zero elementsKerry McLaughlin1-0/+4
2023-10-24[AArch64][GlobalISel] Add support for post-indexed loads/stores. (#69532)Amara Emerson1-0/+2
2023-09-27[GlobalISel] Remove TargetLowering::isConstantUnsignedBitfieldExtractLegalJay Foad1-3/+0
2023-09-25[TargetLowering] Deduplicate choosing InlineAsm constraint between ISels (#67...Nick Desaulniers1-1/+1
2023-09-22[AArch64][GlobalISel] Avoid running the shl(zext(a), C) -> zext(shl(a, C)) co...Amara Emerson1-0/+4
2023-09-16[SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a con...Yingwei Zheng1-1/+0
2023-09-15[TLI] Add extend as explicit parameter to shouldRemoveExtendFromGSIndex [nfc]Philip Reames1-1/+1
2023-09-14[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#6...Arthur Eubanks1-1/+1
2023-09-13reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66264)Nick Desaulniers1-2/+3
2023-09-13Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)"Reid Kleckner1-3/+2
2023-09-13[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)Nick Desaulniers1-2/+3
2023-09-05[AArch64] Remove copy instruction between uaddlv and dupJingu Kang1-0/+3
2023-09-01[AArch64][SME] Don't use OBSCURE_COPY to avoid rematerialization.Sander de Smalen1-7/+0
2023-08-11[AArch64] Remove redundant const from return types (NFC)Kazu Hirata1-2/+2
2023-08-09[AArch64][SVE2] Combine trunc+add+lsr to rshrnbMatt Devereau1-0/+3
2023-07-28[AArch64] Add funnel shift lowering for SelectionDAGTuan Chuong Goh1-3/+0
2023-06-26[AArch64][CodeGen] Lower (de)interleave2 intrinsics to ld2/st2Graham Hunter1-0/+6
2023-06-15[AArch64][SVE] Enable shouldFoldSelectWithIdentityConstant for SVE.David Green1-0/+3
2023-06-02[AArch64] Don't use tbl lowering if ZExt can be folded into user.Florian Hahn1-2/+2
2023-05-30[CodeGen] Refactor IR generation functions to use IRBuilder in ComplexDeinter...Igor Kirillov1-1/+1
2023-05-29[AArch64] Remove unused declaration LowerSCALAR_TO_VECTORKazu Hirata1-1/+0
2023-05-09[CodeGen][KCFI] Move cfi-type lowering to TargetLoweringSami Tolvanen1-0/+4
2023-05-02[AArch64] Add sign bits handling for vector compare nodesDavid Green1-0/+5
2023-04-26[InlineAsm][AArch64]Add backend support for flag output parametersMingming Liu1-0/+6
2023-04-05[AArch64][SME] Fix an infinite loop in DAGCombine related to adding -force-st...Dinar Temirbulatov1-0/+2
2023-04-02[Targets] Rename Flag->Glue. NFCCraig Topper1-3/+3
2023-03-27[LoopVectorize] Don't tail-fold for scalable VFs when there is no scalar tailDavid Sherwood1-1/+1
2023-03-13[AArch64][SVE]: custom lower AVGFloor/AVGCeil.Hassnaa Hamdi1-0/+1
2023-03-10[AArch64] NFC: Merge addTypeForStreamingSVE and addTypeForFixedLengthSVESander de Smalen1-2/+1
2023-02-27[AArch64] Don't remove free sext_inreg(vector_extract(x)) if it leads to mult...David Green1-0/+2
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