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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
2024-06-19[AArch64] Avoid using NEON BSL for streaming[-compatible] functions (#95803)Sander de Smalen1-3/+5
2024-06-19[AArch64] Let patterns for NEON instructions check runtime mode. (#95560)Sander de Smalen1-1/+2
2024-06-18[AArch64] Fix v4i8 loads in strict-align mode. (#95828)Eli Friedman1-0/+4
2024-06-18[AArch64][SME] Remove unused ZA lazy-save (#81648)Matthew Devereau1-50/+110
2024-06-18[AArch64][GISel] Translate legal SVE formal arguments and select COPY for SVE...Him1881-1/+1
2024-06-17[AArch64] Lower extending sitofp using tbl (#92528)Momchil Velikov1-2/+35
2024-06-17[AArch64] Refactor creation of a shuffle mask for TBL (NFC) (#92529)Momchil Velikov1-37/+47
2024-06-14[AArch64] LowerAVG - fallback to default expansion (#95416)Simon Pilgrim1-44/+2
2024-06-13[AArch64][SME] Save VG for unwind info when changing streaming-mode (#83301)Kerry McLaughlin1-0/+12
2024-06-10[clang] Reland Add tanf16 builtin and support for tan constrained intrinsic ...Farzon Lotfi1-8/+8
2024-06-10[AArch64] Push mul into extend operands (#94960)David Green1-36/+44
2024-06-07[arm64] Add tan intrinsic lowering (#94545)Farzon Lotfi1-26/+30
2024-06-04[AArch64] Sink llvm.vscale.i32 into blocks for better isel (#93465)Fangcao Wang1-1/+9
2024-06-03[AArch64] Support preserve_none calling convention (#91046)antangelo1-0/+31
2024-05-31[AArch64][PAC] Lower authenticated calls with ptrauth bundles. (#85736)Ahmed Bougacha1-24/+79
2024-05-31[AArch64] Avoid NEON ctpop in Streaming-SVE mode (#93826)Sander de Smalen1-6/+6
2024-05-30[AArch64][GISel] Support SVE with 128-bit min-size for G_LOAD and G_STORE (#9...Him1881-8/+23
2024-05-29[AArch64] Add patterns for conversions using fixed-point scvtf (#92922)Momchil Velikov1-1/+1
2024-05-29[AArch64] Expand vector ops when NEON and SVE are unavailable. (#90833)Sander de Smalen1-25/+54
2024-05-24[AArch64][SVE] Lower function arguments in types of arrays of predicates (#90...Zhaoshi Zheng1-2/+0
2024-05-23[AArch64] Extend efficient lowering of experimental.cttz.elts (#92114)Hari Limaye1-4/+17
2024-05-22[AArch64][SVE2] UZP should only have one result (#93041)Miguel Saldivar1-4/+2
2024-05-17[AArch64] Avoid using NEON FCVTXN in Streaming-SVE mode. (#91981)Sander de Smalen1-1/+2
2024-05-15Fix typo "indicies" (#92232)Jay Foad1-1/+1
2024-05-15[LLVM][CodeGen][SVE] Improve custom lowering for EXTRACT_SUBVECTOR. (#90963)Paul Walker1-26/+33
2024-05-14[AArch64] Remove redundant FDIV Combine. (#91924)Sander de Smalen1-72/+1
2024-05-14[AArch64] Postcommit fixes for histogram intrinsic (#92095)Graham Hunter1-6/+8
2024-05-14[AArch64] Improve code generation for experimental.cttz.elts (#91505)Hari Limaye1-1/+6
2024-05-13[AArch64] Fix -Wunused-variable in AArch64ISelLowering.cpp (NFC)Jie Fu1-1/+1
2024-05-13[AArch64] Add an all-in-one histogram intrinsicGraham Hunter1-0/+63
2024-05-13[AArch64] Extend v2i64 fptosi.sat to v2f64 (#91714)David Green1-0/+9
2024-05-10ISel/AArch64: custom lower vector ISD::[L]LRINT (#89035)Ramkumar Ramachandra1-4/+39
2024-05-10[AArch64] Combine getActiveLaneMask with vector_extract (#81139)Momchil Velikov1-0/+62
2024-05-10[LLVM][CodeGen][SVE] Clean up lowering of VECTOR_SPLICE operations. (#91330)Paul Walker1-31/+7
2024-05-09[AArch64] Remove EXT instr before UZP when extracting elements from vector (#...Lukacma1-0/+24
2024-05-06[AArch64][GlobalISel] Common some shuffle mask functions.David Green1-67/+32
2024-05-06[AArch64][SelectionDAG] Lower multiplication by a constant to shl+sub+shl+sub...Allen1-0/+30
2024-05-05[AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#...Weihang Fan1-1/+2
2024-05-02[AArch64] Avoid vector interleave instructions when NEON and SVE are unavaila...Sander de Smalen1-13/+14
2024-05-02[llvm][AArch64] Fix Arm 32 bit build warnings (#90862)David Spickett1-3/+3
2024-05-01[LLVM][SVE] Improve legalisation of fixed length get.active.lane.mask (#90213)Paul Walker1-37/+43
2024-04-29Move several vector intrinsics out of experimental namespace (#88748)Maciej Gabka1-2/+2
2024-04-27[AArch64] Lowering of fpmode intrinsics in DAG (#80611)Serge Pavlov1-0/+68
2024-04-25[AArch64] Combine concat(binop, binop) into binop(concat, concat) (#89911)David Green1-7/+5
2024-04-25[AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+addzhongyunde 004434071-2/+33
2024-04-25[AArch64][SelectionDAG] Correct the shift amounts boundzhongyunde 004434071-2/+2
2024-04-24[AArch64] Unify lowering logic for fixed-length vectors. (#89393)Sander de Smalen1-124/+109
2024-04-23[LLVM][CodeGen][AArch64] Simplify lowering for predicate inserts. (#89072)Paul Walker1-10/+8
2024-04-19[AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub. (#88413)Dinar Temirbulatov1-2/+2
2024-04-16[InterleavedAccessPass] Get round the unsupported large scalarize vectors (#8...Allen1-1/+1
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