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2022-12-17[CodeGen] Additional Register argument to ↵Christudasan Devadasan6-15/+18
storeRegToStackSlot/loadRegFromStackSlot With D134950, targets get notified when a virtual register is created and/or cloned. Targets can do the needful with the delegate callback. AMDGPU propagates the virtual register flags maintained in the target file itself. They are useful to identify a certain type of machine operands while inserting spill stores and reloads. Since RegAllocFast spills the physical register itself, there is no way its virtual register can be mapped back to retrieve the flags. It can be solved by passing the virtual register as an additional argument. This argument has no use when the spill interfaces are called during the greedy allocator or even the PrologEpilogInserter and can pass a null register in such cases. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138656
2022-12-17[CodeGen] Use cloneVirtualRegister in LiveIntervals and LiveRangeEditChristudasan Devadasan2-4/+3
It is needed to invoke the delegate methods effectively whenever a virtual register is cloned from an existing register of the same class. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D138517
2022-12-17[CodeGen] Use delegate to notify targets when virtual registers are createdChristudasan Devadasan1-6/+4
This will help targets to customize certain codegen decisions based on the virtual registers involved in special operations. This patch also extends the existing delegate in MRI to start support multicast. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D134950
2022-12-16[CodeGen] std::optional::value => operator*/operator->Fangrui Song7-26/+24
value() has undesired exception checking semantics and calls __throw_bad_optional_access in libc++. Moreover, the API is unavailable without _LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS). This fixes LLVMMIRParser, LLVMGlobalISel, LLVMAsmPrinter, LLVMSelectionDAG.
2022-12-16[Transforms,CodeGen] std::optional::value => operator*/operator->Fangrui Song7-31/+31
value() has undesired exception checking semantics and calls __throw_bad_optional_access in libc++. Moreover, the API is unavailable without _LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS).
2022-12-16Correct typos (NFC)Sprite2-3/+3
Just found some typos while reading the llvm/circt project. compliment -> complement emitsd -> emits
2022-12-16[PowerPC] Fix up memory ordering after combining BV to a loadNemanja Ivanovic1-1/+1
The combiner for BUILD_VECTOR that merges consecutive loads into a wide load had two issues: - It didn't check that the input loads all have the same input chain - It didn't update nodes that are chained to the original loads to be chained to the new load This caused issues with bootstrap when 3c4d2a03968ccf5889bacffe02d6fa2443b0260f was committed. This patch fixes the issue so it can unblock this commit. Differential revision: https://reviews.llvm.org/D140046
2022-12-16[Support] llvm::Optional => std::optionalFangrui Song2-5/+5
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-15[SelectionDAG] Give all the target specific subclasses of SelectionDAGISel ↵Craig Topper1-3/+2
their own pass ID. Previously we had a shared ID in SelectionDAGISel. AMDGPU has an initializePass function for its subclass of SelectionDAGISel. No other target does. This causes all target specific SelectionDAGISel passes to be known as "amdgpu-isel". I'm not sure what would happen if another target tried to implement an initializePass function too since the ID is already claimed. This patch gives all targets their own ID and passes it down to SelectionDAGISel constructor to MachineFunctionPass's constructor. Unfortunately, I think this causes most targets to lose print-before/after-all support for their SelectionDAGISel pass. And they probably no longer support start/stop-before/after. We can add initializePass functions to fix this as a follow up. NOTE: This was probably also broken if the AMDGPU target isn't compiled in. Step 1 to fixing PR59538. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D140161
2022-12-15[mlgo] Retire LLVM_HAVE_TF_APIKazu Hirata1-2/+2
I've eliminated all uses of LLVM_HAVE_TF_API except a couple of them being removed in llvm/lib/CodeGen/CMakeLists.txt. This patch removes remaining definitions and uses of LLVM_HAVE_TF_API. Differential Revision: https://reviews.llvm.org/D140169
2022-12-15[NFC] Rename Instruction::insertAt() to Instruction::insertInto(), to be ↵Vasileios Porpodas1-2/+2
consistent with BasicBlock::insertInto() Differential Revision: https://reviews.llvm.org/D140085
2022-12-15Revert "Revert "[AArch64][GlobalISel][Legalizer] Legalize G_SHUFFLE_VECTOR ↵Kevin Athey1-3/+71
with different lengths"" This reverts commit 192cc76e0be688106492989cd845ba786a7ae36d. Reverted Revert, as build was fixed while I was examining.
2022-12-15Revert "[AArch64][GlobalISel][Legalizer] Legalize G_SHUFFLE_VECTOR with ↵Kevin Athey1-71/+3
different lengths" This reverts commit 4c52fb1a5ee20846627d16e38f5dec08c08f8884. Breaks sanitizer ubsan buildbot: https://lab.llvm.org/buildbot/#/builders/85/builds/12983
2022-12-15Revert "[SelectionDAG] Do not second-guess alignment for alloca"Ron Lieberman1-1/+14
Breaks amdgpu buildbot https://lab.llvm.org/buildbot/#/builders/193 23491 This reverts commit ffedf47d8b793e07317f82f9c2a5f5425ebb71ad.
2022-12-15[MRI] Print more debug infor in clearVirtRegs() (NFC)Nikita Popov1-1/+5
2022-12-15[SelectionDAG] Do not second-guess alignment for allocaAndrew Savonichev1-14/+1
Alignment of an alloca in IR can be lower than the preferred alignment on purpose, but this override essentially treats the preferred alignment as the minimum alignment. The patch changes this behavior to always use the specified alignment. If alignment is not set explicitly in LLVM IR, it is set to DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign. Tests are changed as well: explicit alignment is increased to match the preferred alignment if it changes output, or omitted when it is hard to determine the right value (e.g. for pointers, some structs, or weird types). Differential Revision: https://reviews.llvm.org/D135462
2022-12-15Reland "[TargetLowering] Teach DemandedBits about VSCALE"Benjamin Maxwell1-0/+17
Reland with a fixup to avoid converting APInts to int64_t which allowed for overflows (UB) with sufficiently high/low multiplier values. This allows DemandedBits to see the result of VSCALE will be at most VScaleMax * some compile-time constant. This relies on the vscale_range() attribute being present on the function, with a max set. (This is done by default when clang is targeting AArch64+SVE). Using this various redundant operations (zexts, sexts, ands, ors, etc) can be eliminated. Differential Revision: https://reviews.llvm.org/D138508
2022-12-15[DAGCombine] Fix always true condition in combineShiftToMULHJuan Manuel MARTINEZ CAAMAÑO1-1/+1
Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D139550
2022-12-15[AArch64][GlobalISel][Legalizer] Legalize G_SHUFFLE_VECTOR with different ↵Vladislav Dzhidzhoev1-3/+71
lengths Legalize G_SHUFFLE_VECTOR having destination vector length greater than source vector length by reshaping source vectors. Partial implementation of SelectionDAGBuilder::visitShuffleVector. Differential Revision: https://reviews.llvm.org/D132190
2022-12-15Revert "[TargetLowering] Teach DemandedBits about VSCALE"Benjamin Maxwell1-18/+0
This reverts commit c165b0553a96394b9bbf3984782703cdae99821d.
2022-12-14Don't include Optional.hKazu Hirata9-9/+0
These files no longer use llvm::Optional.
2022-12-14[llvm][DebugInfo] Backport DW_AT_default_value for template argsMichael Buch2-2/+10
**Summary** Starting with DWARFv5, DW_AT_default_value can be used to indicate that a template argument has a default value. With this patch LLVM will emit the this attribute earlier versions of DWARF, unless compiling with -gstrict-dwarf. Differential Revision: https://reviews.llvm.org/D139953
2022-12-14[EarlyIfConversion] Add target hook to allow for multiple ifcvt iterations.Hendrik Greving1-3/+9
Adds a target hook canPredicatePredicatedInstr(const MachineInstr&) that assumes an instruction is already predicated and returns true if it can be predicated again, used by the early if-conversion pass in order to iterate multiple times on architectures supporting predicate logic. No test added since there is no upstream target that can take advantage. Differential Revision: https://reviews.llvm.org/D139981
2022-12-14Attributes: Add function getter to parse integer string attributesMatt Arsenault2-14/+10
The most common case for string attributes parses them as integers. We don't have a convenient way to do this, and as a result we have inconsistent missing attribute and invalid attribute handling scattered around. We also have inconsistent radix usage to getAsInteger; some places use the default 0 and others use base 10. Update a few of the uses, but there are quite a lot of these.
2022-12-14[TargetLowering] Teach DemandedBits about VSCALEBenjamin Maxwell1-0/+18
This allows DemandedBits to see the result of VSCALE will be at most VScaleMax * some compile-time constant. This relies on the vscale_range() attribute being present on the function, with a max set. (This is done by default when clang is targeting AArch64+SVE). Using this various redundant operations (zexts, sexts, ands, ors, etc) can be eliminated. Differential Revision: https://reviews.llvm.org/D138508
2022-12-14[Analysis] llvm::Optional => std::optionalFangrui Song1-2/+1
2022-12-14[VP][RISCV] Add vp.ctpop and RISC-V support.Yeting Kuo3-0/+65
The patch also adds expandVPCTPOP in TargetLowering to expand VP_CTPOP nodes. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139920
2022-12-13[X86] Don't zero out %eax if both %al and %ah are usedBill Wendling1-1/+7
The iterator over super and sub registers doesn't include both 8-bit registers in its list. So if both registers are used and only one of them is live on return, then we need to make sure that the other 8-bit register is also marked as live and not zeroed out. Reviewed By: nickdesaulniers Differential Revision: https://reviews.llvm.org/D139679
2022-12-13Revert "[Propeller] Use Fixed MBB ID instead of volatile ↵Rahman Lavaee8-111/+49
MachineBasicBlock::Number." This reverts commit 6015a045d768feab3bae9ad9c0c81e118df8b04a. Differential Revision: https://reviews.llvm.org/D139952
2022-12-13[AMDGPU] Add bf16 storage supportPierre van Houtryve3-5/+37
- [Clang] Declare AMDGPU target as supporting BF16 for storage-only purposes on amdgcn - Add Sema & CodeGen tests cases. - Also add cases that D138651 would have covered as this patch replaces it. - [AMDGPU] Add BF16 storage-only support - Support legalization/dealing with bf16 operations in DAGIsel. - bf16 as a type remains illegal and is represented as i16 for storage purposes. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D139398
2022-12-13[NFC] Add checks for potential null returnsPhoebe Wang3-1/+3
2022-12-13[CodeGen] llvm::Optional => std::optionalFangrui Song35-248/+262
2022-12-12DebugInfo: Test DW_AT_prototyped and generalize it to handle C11 and C17David Blaikie1-8/+2
2022-12-12[NFC] Cleanup: Replaces BB->getInstList().insert() with I->insertAt().Vasileios Porpodas1-2/+2
This is part of a series of cleanup patches towards making BasicBlock::getInstList() private. Differential Revision: https://reviews.llvm.org/D138877
2022-12-12[mlgo] Use LLVM_HAVE_TFLITE instead of LLVM_HAVE_TF_API in C++ code (NFC)Kazu Hirata4-22/+22
We use LLVM_HAVE_TFLITE as the key to enable the mlgo work these days, and LLVM_HAVE_TF_API is defined whenever LLVM_HAVE_TF_API is defined. I'm posting this patch because it's purely mechanical. I'll post a follow-up patch to remove LLVM_HAVE_TF_API in non-C++ files, and that will not be as mechanical as this one. Differential Revision: https://reviews.llvm.org/D139863
2022-12-12[ARM][CodeGen] Add integer support for complex deinterleavingNicholas Guy1-9/+21
Differential Revision: https://reviews.llvm.org/D139628
2022-12-12[DAGCombine] Fold Splat(bitcast(buildvector(x,..))) to splat(x)David Green1-0/+17
This adds a fold which teaches the backend to fold splat(bitcast(buildvector(x,..))) or splat(bitcast(scalar_to_vector(x))) to a single splat. This only handles lane 0 splats, which are only valid under LE, and needs to be a little careful with the types it creates for the new buildvector. Differential Revision: https://reviews.llvm.org/D139611
2022-12-12[AA] Remove CFL AA passesNikita Popov1-30/+0
The CFL Steens/Anders alias analysis passes are not enabled by default, and to the best of my knowledge have no pathway towards ever being enabled by default. The last significant interest in these passes seems to date back to 2016. Given the little maintenance these have seen in recent times, I also have very little confidence in the correctness of these passes. I don't think we should keep these in-tree. Differential Revision: https://reviews.llvm.org/D139703
2022-12-12[DAGCombiner] Scalarize extend/truncate for splat vector.jacquesguan1-0/+46
This revision scalarizes extend/truncate for splat vector. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D122875
2022-12-12[NFC] Update comment for TRUNC followed by a masked storeXiang1 Zhang1-1/+1
2022-12-12[VP][RISCV] Add vp.bitreverse and RISC-V support.Yeting Kuo3-0/+70
The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D139697
2022-12-12[DAG] Stop combine for masked compressstoreXiang1 Zhang1-2/+3
Reviewed By: WangPengfei Differential Revision: https://reviews.llvm.org/D139682
2022-12-12[StackProtector] Rewrite dominator tree update handlingRoman Lebedev1-52/+29
2022-12-12Enhance stack protectorXiang1 Zhang1-14/+55
Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D139254
2022-12-11Use poison instead of undef where its used as a placeholder [NFC]Manuel Brito1-1/+1
Differential Revision: https://reviews.llvm.org/D139789
2022-12-10[llvm] Use std::optional instead of None in comments (NFC)Kazu Hirata1-1/+1
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-10Don't include None.h (NFC)Kazu Hirata12-12/+0
I've converted all known uses of None to std::nullopt, so we no longer need to include None.h. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-09[llvm] Use std::nullopt instead of None (NFC)Kazu Hirata1-8/+9
This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-09Allow epilogue_begin to be emitted when generating DWARFAriel Burton2-3/+14
We identify epilogue code by looking for instructions tagged with FrameDestroy. A function may have more than one epilogue, e.g., because of early returns or code duplicated during optimization. We need only track the current block, and emit epilogie_begin at most once per block. We reduce the number of entries in the line table by combining epilogue_begin with other flags instead of emitting a separate entry just for epilogue_begin. Reviewed By: dblaikie, aprantl Differential Revision: https://reviews.llvm.org/D133376
2022-12-09[WebAssembly] Print DEBUG_VALUE once for target indicesHeejin Ahn1-2/+0
`DEBUG_VALUE` comments are printed before an instruction, so they are not printed with `AddComment` method as other comments are, but printed using `emitRawComment` method. But currently `emitDebugValueComment` calls `emitRawComment` twice for target-index-based `DBG_VALUE`s: once in the `switch`-`case`, https://github.com/llvm/llvm-project/blob/d77ae7f2513504655e555cd326208598093d66e2/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp#L1192-L1193 and again at the end of the method: https://github.com/llvm/llvm-project/blob/d77ae7f2513504655e555cd326208598093d66e2/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp#L1227-L1228 This makes them printed twice. I think this happened through multiple commits modifying and refactoring this method. Reviewed By: dschuff Differential Revision: https://reviews.llvm.org/D139579
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