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path: root/llvm/lib/CodeGen/TargetSchedule.cpp
AgeCommit message (Expand)AuthorFilesLines
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-1/+1
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-06-05[CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel1-5/+7
2018-05-31[MCSchedule] Add the ability to compute the latency and throughput informatio...Andrea Di Biagio1-1/+15
2018-04-15[MC] Moved all the remaining logic that computed instruction latency and reci...Andrea Di Biagio1-35/+10
2018-04-08[TargetSchedule] shrink interface for init(); NFCISanjay Patel1-6/+4
2018-03-13[MC] Move the reciprocal throughput computation from TargetSchedModel to MCSc...Andrea Di Biagio1-29/+4
2018-03-13[MC] Move the instruction latency computation from TargetSchedModel to MCSche...Andrea Di Biagio1-9/+1
2018-03-11[TargetSchedule] Minor refactor in computeInstrLatency. NFCAndrea Di Biagio1-6/+4
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-2/+2
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie1-1/+1
2017-10-10CodeGen: Minor cleanups to use MachineInstr::getMF. NFCJustin Bogner1-1/+1
2017-07-26This patch returns proper value to indicate the case when instruction through...Andrew V. Tischenko1-20/+24
2017-06-06Fix spelling mistake in getRThroughput static function names. NFCI.Simon Pilgrim1-11/+11
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
2017-04-14This patch closes PR#32216: Better testing of schedule model instruction late...Andrew V. Tischenko1-1/+70
2017-03-27Improve machine schedulers for in-order processorsJaved Absar1-0/+23
2017-02-27[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko1-3/+13
2016-08-24TargetSchedule: Do not consider subregister definitions as reads.Matthias Braun1-1/+1
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith1-10/+10
2016-06-21[TargetSchedule] Use 'isOutOfOrder' as possible to avoid magic number. NFC.Junmo Park1-3/+2
2016-02-23CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith1-1/+1
2016-01-05[MISched] Explanatory error message when machine model is not complete. NFCMinSeong Kim1-1/+1
2015-07-17Use llvm_unreachable() instead of report_fatal_error() if the machine model i...Matthias Braun1-5/+3
2015-05-14Turn effective assert(0) into llvm_unreachableMatthias Braun1-3/+1
2015-05-14TargetSchedule: factor out common code; NFCMatthias Braun1-21/+17
2014-10-14Remove unnecessary TargetMachine.h includes.Eric Christopher1-1/+0
2014-09-02Change MCSchedModel to be a struct of statically initialized data.Pete Cooper1-4/+4
2014-08-05Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher1-2/+1
2014-08-04Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher1-1/+2
2014-08-03MachineCombiner Pass for selecting faster instructionGerolf Hoflehner1-0/+22
2014-06-26Revert "Introduce a string_ostream string builder facilty"Alp Toker1-4/+5
2014-06-26Introduce a string_ostream string builder faciltyAlp Toker1-5/+4
2013-09-30IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer1-2/+5
2013-09-25Mark the x86 machine model as incomplete. PR17367.Andrew Trick1-1/+2
2013-06-17MI-Sched: handle ReadAdvance latencies as used by Swift.Andrew Trick1-1/+4
2013-06-15Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick1-44/+14
2013-04-13MI-Sched cleanup. If an instruction has no valid sched class, do not attempt ...Andrew Trick1-0/+2
2013-03-16Change the default latency for implicit defs.Andrew Trick1-1/+4
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth1-2/+2
2012-11-06misched: TargetSchedule interface for machine resources.Andrew Trick1-4/+35
2012-10-17misched: Better handling of invalid latencies in the machine modelAndrew Trick1-2/+10
2012-10-11misched: Handle "transient" non-instructions.Andrew Trick1-17/+23
2012-10-10misched: fall-back to a target hook for instr bundles.Andrew Trick1-3/+4
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick1-0/+49
2012-10-09misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick1-0/+24
2012-10-09misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ex...Andrew Trick1-6/+12
2012-10-04Enable -schedmodel, but prefer itineraries until we have more benchmark data.Andrew Trick1-52/+51
2012-09-18TargetSchedule: cleanup computeOperandLatency logic & diagnostics.Andrew Trick1-6/+16
2012-09-18TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick1-0/+140
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