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path: root/llvm/lib/CodeGen/TargetRegisterInfo.cpp
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2020-02-03[TargetRegisterInfo] Make the heuristic to skip region split overridable by t...Quentin Colombet1-1/+21
2019-09-13[TargetRegisterInfo] Remove SVT argument from getCommonSubClass.Craig Topper1-13/+5
2019-08-13Eliminate implicit Register->unsigned conversions in VirtRegMap. NFCDaniel Sanders1-1/+1
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-14/+15
2019-07-31Reland "[DwarfDebug] Dump call site debug info"Djordje Todorovic1-0/+13
2019-07-12Revert "[DwarfDebug] Dump call site debug info"Djordje Todorovic1-14/+0
2019-07-09[DwarfDebug] Dump call site debug infoDjordje Todorovic1-0/+14
2019-03-11[RegAlloc] Avoid compile time regression with multiple copy hints.Jonas Paulsson1-0/+6
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen1-1/+2
2018-05-01Remove \brief commands from doxygen comments.Adrian Prantl1-1/+1
2018-04-30IWYU for llvm-config.h in llvm, additions.Nico Weber1-0/+1
2018-03-30[MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi1-4/+10
2018-03-23Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie1-1/+1
2018-03-23Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda1-0/+23
2018-03-19Revert [MachineLICM] This reverts commit rL327856Zaara Syeda1-23/+0
2018-03-19[MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda1-0/+23
2018-02-02[GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.Aditya Nandakumar1-0/+22
2018-01-31Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi1-3/+3
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun1-5/+5
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih1-0/+15
2017-12-05[Regalloc] Generate and store multiple regalloc hints.Jonas Paulsson1-25/+30
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih1-2/+5
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih1-2/+2
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih1-3/+5
2017-11-28[CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih1-7/+7
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-3/+3
2017-11-10[RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.Jonas Paulsson1-4/+5
2017-11-03Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie1-1/+1
2017-10-15Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman1-1/+1
2017-10-12[dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton1-1/+1
2017-09-14TableGen support for parameterized register class informationKrzysztof Parzyszek1-2/+5
2017-06-19[Target] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko1-5/+15
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
2017-05-17BitVector: add iterators for set bitsFrancis Visoiu Mistrih1-2/+1
2017-04-24Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek1-3/+3
2017-04-24Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek1-2/+2
2017-04-24Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek1-2/+2
2017-04-24Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek1-5/+5
2017-02-24Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin1-9/+0
2017-02-23Correct register pressure calculation in presence of subregsStanislav Mekhanoshin1-0/+9
2017-01-28Cleanup dump() functions.Matthias Braun1-3/+3
2017-01-25Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFCKrzysztof Parzyszek1-6/+4
2016-12-15Extract LaneBitmask into a separate typeKrzysztof Parzyszek1-8/+2
2016-11-30Clarify rules for reserved regs, fix aarch64 ones.Matthias Braun1-0/+30
2016-08-11Use the range variant of find instead of unpacking begin/endDavid Majnemer1-1/+1
2016-07-28MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun1-2/+2
2016-04-08[TargetRegisterInfo] Re-apply r265734.Quentin Colombet1-12/+5
2016-04-08Revert "[TargetRegisterInfo] Refactor the code to use BitMaskClassIterator."Quentin Colombet1-5/+12
2016-04-07[TargetRegisterInfo] Refactor the code to use BitMaskClassIterator.Quentin Colombet1-12/+5
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