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path: root/llvm/lib/CodeGen/SelectionDAG
AgeCommit message (Expand)AuthorFilesLines
2020-02-08[LegalizeTypes][ARM][AArch64][PowerPC][RISCV][X86] Use BUILD_PAIR to return e...Craig Topper1-11/+0
2020-02-07[LegalizeDAG][X86][AMDGPU] Use ANY_EXTEND instead of ZERO_EXTEND when promoti...Craig Topper1-2/+7
2020-02-07[MachineInstr] Add isCandidateForCallSiteEntry predicateVedant Kumar1-1/+2
2020-02-07[NFC] Introduce an API for MemOpGuillaume Chatelet1-15/+11
2020-02-06Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field"Jeremy Morse3-19/+16
2020-02-06Revert "[DebugInfo][DAG] Distinguish different kinds of location indirection"Jeremy Morse1-19/+5
2020-02-06Revert "[SafeStack][DebugInfo] Insert DW_OP_deref in correct location"Jeremy Morse1-3/+3
2020-02-05visitINSERT_VECTOR_ELT - pull out repeated dyn_cast. NFCI.Simon Pilgrim1-4/+3
2020-02-04Revert "[WebAssembly][InstrEmitter] Foundation for multivalue call lowering"Thomas Lively1-9/+3
2020-02-04[SEH] Remove CATCHPAD SDNode and X86::EH_RESTORE MachineInstrReid Kleckner1-5/+0
2020-02-04Separately track input and output denormal modeMatt Arsenault1-11/+14
2020-02-04[DAG] OptLevelChanger - fix uninitialized variable analyzer warning (PR44471)Simon Pilgrim1-1/+1
2020-02-04[ARM][VecReduce] Force expand vector_reduce_fminDavid Green1-2/+2
2020-02-04[NFC] Encapsulate MemOp logicGuillaume Chatelet1-6/+6
2020-02-03[TargetLowering] SimplifyDemandedBits - add basic KnownBits ZEXTLoad handlingSimon Pilgrim1-0/+6
2020-02-03[Alignment][NFC] Use Align for getMemcpy/Memmove/MemsetGuillaume Chatelet2-47/+37
2020-02-03[Alignment][NFC] Use Align for code creating MemOpGuillaume Chatelet1-58/+63
2020-02-03Fix broken invariantGuillaume Chatelet1-5/+7
2020-02-01[LegalizeTypes][X86] Add a new strategy for type legalizing f16 type that sof...Craig Topper7-3/+485
2020-01-31DAG: Check if a value is divergent before requiresUniformRegisterMatt Arsenault1-2/+2
2020-01-31[DAG] SimplifyMultipleUseDemandedBits - peek through unused ISD::INSERT_SUBVE...Simon Pilgrim1-0/+12
2020-01-31[DAG] Enable ISD::INSERT_SUBVECTOR SimplifyMultipleUseDemandedBits handlingSimon Pilgrim1-0/+16
2020-01-31[NFC] Introduce a type to model memory operationGuillaume Chatelet2-36/+22
2020-01-30[SafeStack][DebugInfo] Insert DW_OP_deref in correct locationLeonard Chan1-3/+3
2020-01-30Revert "[SafeStack][DebugInfo] Insert DW_OP_deref in correct location"Leonard Chan1-3/+3
2020-01-30[SafeStack][DebugInfo] Insert DW_OP_deref in correct locationLeonard Chan1-3/+3
2020-01-30[DAGCombiner] ISD::AND/OR/XOR - use general SelectionDAG::FoldConstantArithmeticSimon Pilgrim1-10/+16
2020-01-30[DAGCombiner] ISD::SDIV/UDIV/SREM/UREM - use general SelectionDAG::FoldConsta...Simon Pilgrim1-12/+10
2020-01-29[DAGCombiner] ISD::SHL/SRA/SRL - use general SelectionDAG::FoldConstantArithm...Simon Pilgrim1-12/+6
2020-01-29[DAGCombiner] ISD::MUL - use general SelectionDAG::FoldConstantArithmeticSimon Pilgrim1-14/+8
2020-01-29[DAGCombiner] Sub/SUBSAT - use general SelectionDAG::FoldConstantArithmeticSimon Pilgrim1-10/+7
2020-01-29[DAGCombiner] visitIMINMAX - use general SelectionDAG::FoldConstantArithmeticSimon Pilgrim1-6/+4
2020-01-28Make llvm::StringRef to std::string conversions explicit.Benjamin Kramer2-2/+2
2020-01-28[FPEnv] Add pragma FP_CONTRACT support under strict FP.Wang, Pengfei1-25/+47
2020-01-28[instrinsics] Add @llvm.memcpy.inline instrinsicsGuillaume Chatelet1-1/+22
2020-01-27[DAG] Enable ISD::EXTRACT_SUBVECTOR SimplifyMultipleUseDemandedBits handlingSimon Pilgrim1-0/+11
2020-01-27[FPEnv] Divide macro INSTRUCTION into INSTRUCTION and DAG_INSTRUCTION,Wang, Pengfei4-8/+8
2020-01-26[TargetLowering] Respect recursive depth in SimplifyDemandedBits call to Comp...Simon Pilgrim1-1/+2
2020-01-25[SelectionDAG] ComputeNumSignBits - add DemandedElts support for MIN/MAX opsSimon Pilgrim1-4/+4
2020-01-25[SelectionDAG] ComputeNumSignBits - add support for rotate non-uniform vector...Simon Pilgrim1-1/+2
2020-01-25[SelectionDAG] ComputeNumSignBits - add support for rotate uniform vector amo...Simon Pilgrim1-1/+1
2020-01-25[TargetLowering] SimplifyDemandedBits - Remove ashr if all our demandedbits a...Simon Pilgrim1-0/+7
2020-01-24[SelectionDag] Updated FoldConstantArithmetic method signature in preparation...@justice_adams (Justice Adams)2-37/+39
2020-01-24[DAGCombiner] Add combine for (not (strict_fsetcc)) to create a strict_fsetcc...Craig Topper1-4/+33
2020-01-24Allow combining of extract_subvector to extract elementStanislav Mekhanoshin1-0/+7
2020-01-24[Alignment][NFC] Deprecate Align::None()Guillaume Chatelet1-2/+2
2020-01-24[SelectionDAG] rot(x, y) --> x iff ComputeNumSignBits(x) == BitWidth(x)Simon Pilgrim3-1/+19
2020-01-23[SelectionDAG] ComputeNumSignBits - add ISD::ADD demanded elts supportSimon Pilgrim1-4/+6
2020-01-23[SelectionDAG] ComputeNumSignBits - add ISD::ADD vector supportSimon Pilgrim1-8/+7
2020-01-23[SelectionDAG] ComputeNumSignBits - add ISD::SUB demanded elts supportSimon Pilgrim1-7/+9
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