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path: root/llvm/lib/CodeGen/MachineRegisterInfo.cpp
AgeCommit message (Expand)AuthorFilesLines
2020-01-30CodeGen: Use RegisterMatt Arsenault1-31/+31
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-6/+6
2019-06-25[Peephole] Allow folding loads into instructions w/multiple uses (such as tes...Philip Reames1-0/+7
2019-06-24CodeGen: Introduce a class for registersMatt Arsenault1-3/+3
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-10-20[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)Roman Tereshin1-33/+22
2018-10-03Re-commit: [globalisel] Add a combiner helpers for extending loads and use th...Daniel Sanders1-0/+10
2018-07-30Remove trailing spaceFangrui Song1-1/+1
2018-05-23[GlobalISel] NFCI, Getting GlobalISel ~5% fasterRoman Tereshin1-10/+4
2018-04-30IWYU for llvm-config.h in llvm, additions.Nico Weber1-0/+1
2018-04-03Adding optional Name parameter to createVirtualRegister and createGenericVirt...Puyan Lotfi1-4/+5
2018-03-30[MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi1-1/+2
2018-01-18GlobalISel: Make MachineCSE runnable in the middle of the GlobalISelJustin Bogner1-7/+50
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun1-1/+1
2017-11-28[CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih1-4/+4
2017-11-20[MachineCSE] Add new callback for is caller preserved or constant physregsTony Jiang1-0/+7
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-2/+2
2017-11-16[MachineRegisterInfo] Avoid having dbg.values affect code generationMikael Holmen1-2/+2
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie1-1/+1
2017-10-15Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman1-1/+1
2017-10-12[dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton1-1/+1
2017-09-01LiveIntervalAnalysis: Fix alias regunit reserved definitionMatthias Braun1-0/+18
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
2017-03-19[MIR] Support Customed Register Mask and CSRsOren Ben Simhon1-0/+12
2017-03-16Fixing typos.Oren Ben Simhon1-4/+5
2017-03-14[CodeGen] Fix -Wreorder warning.Benjamin Kramer1-3/+3
2017-03-14Disable Callee Saved RegistersOren Ben Simhon1-2/+34
2017-02-17[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko1-7/+20
2017-01-28Cleanup dump() functions.Matthias Braun1-2/+2
2016-11-08GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover1-11/+0
2016-10-28MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun1-2/+1
2016-10-11Fix warning; NFCMatthias Braun1-2/+2
2016-10-11MIRParser: generic register operands with typesMatthias Braun1-1/+2
2016-10-11MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun1-7/+10
2016-09-27[TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().Geoff Berry1-1/+5
2016-09-15GlobalISel: remove "unsized" LLTTim Northover1-1/+1
2016-09-12GlobalISel: disambiguate types when printing MIRTim Northover1-2/+0
2016-09-09GlobalISel: move type information to MachineRegisterInfo.Tim Northover1-14/+14
2016-08-24MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/...Matthias Braun1-1/+6
2016-07-27[GlobalISel] Introduce an instruction selector.Ahmed Bougacha1-0/+14
2016-07-19[GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha1-2/+5
2016-07-11[IPRA] Properly compute register usage at call sites.Chad Rosier1-2/+3
2016-04-11Replace MachineRegisterInfo::TracksLiveness with a MachineFunctionPropertyDerek Schuff1-2/+1
2016-04-07[MachineRegisterInfo] Track register bank for virtual registers.Quentin Colombet1-1/+6
2016-04-04Replace MachineRegisterInfo::isSSA() with a MachineFunctionPropertyDerek Schuff1-2/+2
2016-03-07[MachineRegisterInfo] Add a method to set the size of a virtual register a po...Quentin Colombet1-0/+4
2016-03-07[MachineRegisterInfo] Get rid of the global-isel ifdefs.Quentin Colombet1-6/+3
2016-02-11[GlobalISel][MachineRegisterInfo] Add a method to create generic vregs.Quentin Colombet1-0/+16
2016-02-10[GlobalISel] Remember the size of generic virtual registersQuentin Colombet1-0/+9
2015-12-02Scheduler / Regalloc: use unique_ptr[] instead of std::vectorFiona Glaser1-4/+3
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