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path: root/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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2024-03-11[CodeGen] Remove unused MachineRegisterInfo methodsJay Foad1-12/+0
2024-03-11[CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770)Jay Foad1-11/+8
2024-02-05AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)Petar Avramovic1-0/+9
2024-01-24Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#79274)Petar Avramovic1-11/+0
2024-01-24AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#78482)Petar Avramovic1-0/+11
2023-10-24[ADT] Rename llvm::erase_value to llvm::erase (NFC) (#70156)Kazu Hirata1-1/+1
2023-08-13[CodeGen] MachineRegisterInfo::constrainRegAttrs - add explicit auto referenc...Simon Pilgrim1-2/+2
2023-04-18[MC] Simplify uses of subregs/superregs. NFC.Jay Foad1-9/+2
2023-04-18[MC] Use subregs/superregs instead of MCSubRegIterator/MCSuperRegIterator. NFC.Jay Foad1-3/+2
2023-04-17[nfc][llvm] Replace pointer cast functions in PointerUnion by llvm casting fu...Shraiysh Vaishay1-5/+5
2023-01-13[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFCCraig Topper1-2/+2
2022-12-17[CodeGen] Use delegate to notify targets when virtual registers are createdChristudasan Devadasan1-6/+4
2022-12-15[MRI] Print more debug infor in clearVirtRegs() (NFC)Nikita Popov1-1/+5
2022-09-15[AMDGPU] Always select s_cselect_b32 for uniform 'select' SDNodeAlexander Timofeev1-4/+4
2022-07-27Use hasNItemsOrLess() in MRI::hasAtMostUserInstrs().Amara Emerson1-6/+2
2022-07-27[AArch64][GlobalISel] Add heuristics for localizing G_CONSTANT.Amara Emerson1-0/+10
2022-03-16Cleanup codegen includesserge-sans-paille1-1/+0
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-0/+1
2022-03-10Cleanup codegen includesserge-sans-paille1-1/+0
2022-02-08[X86] Implement -fzero-call-used-regs optionBill Wendling1-0/+15
2022-01-30[CodeGen] Use default member initialization (NFC)Kazu Hirata1-2/+1
2021-10-31[CodeGen] Use make_early_inc_range (NFC)Kazu Hirata1-3/+1
2021-06-14[AIX][XCOFF] emit vector info of traceback table.zhijian1-2/+3
2021-03-05Reapply "[DebugInfo] Add new instruction and DIExpression operator for varia...Stephen Tozer1-3/+3
2021-03-04Revert "[DebugInfo] Add new instruction and DIExpression operator for variadi...Stephen Tozer1-3/+3
2021-03-04[DebugInfo] Add new instruction and DIExpression operator for variadic debug ...gbtozers1-3/+3
2021-02-20[CodeGen] Use range-based for loops (NFC)Kazu Hirata1-7/+4
2021-02-19[CodeGen] Use range-based for loops (NFC)Kazu Hirata1-8/+8
2021-01-21[CodeGen] Use llvm::append_range (NFC)Kazu Hirata1-2/+1
2021-01-20[llvm] Use hasSingleElement (NFC)Kazu Hirata1-8/+2
2021-01-07[CodeGen] Remove unused function isCallerPreservedOrConstPhysReg (NFC)Kazu Hirata1-7/+0
2020-12-13[CodeGen] Use llvm::erase_value (NFC)Kazu Hirata1-2/+1
2020-10-28[NFC] Use [MC]Register in CSE & LICMGaurav Jain1-1/+1
2020-06-22[DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructionsstozer1-1/+1
2020-04-07CodeGen: Use Register in more placesMatt Arsenault1-6/+6
2020-04-06Revert "[IPRA][ARM] Spill extra registers at -Oz"Oliver Stannard1-37/+13
2020-03-18[IPRA][ARM] Spill extra registers at -OzOliver Stannard1-13/+37
2020-01-30CodeGen: Use RegisterMatt Arsenault1-31/+31
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-6/+6
2019-06-25[Peephole] Allow folding loads into instructions w/multiple uses (such as tes...Philip Reames1-0/+7
2019-06-24CodeGen: Introduce a class for registersMatt Arsenault1-3/+3
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-10-20[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)Roman Tereshin1-33/+22
2018-10-03Re-commit: [globalisel] Add a combiner helpers for extending loads and use th...Daniel Sanders1-0/+10
2018-07-30Remove trailing spaceFangrui Song1-1/+1
2018-05-23[GlobalISel] NFCI, Getting GlobalISel ~5% fasterRoman Tereshin1-10/+4
2018-04-30IWYU for llvm-config.h in llvm, additions.Nico Weber1-0/+1
2018-04-03Adding optional Name parameter to createVirtualRegister and createGenericVirt...Puyan Lotfi1-4/+5
2018-03-30[MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi1-1/+2
2018-01-18GlobalISel: Make MachineCSE runnable in the middle of the GlobalISelJustin Bogner1-7/+50
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