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path: root/llvm/lib/CodeGen/MachineOperand.cpp
AgeCommit message (Expand)AuthorFilesLines
2020-01-24[Alignment][NFC] Deprecate Align::None()Guillaume Chatelet1-2/+1
2020-01-17Remove unneeded FoldingSet.h include from Attributes.hReid Kleckner1-0/+1
2020-01-13[GlobalISel] Change representation of shuffle masks in MachineOperand.Eli Friedman1-6/+6
2020-01-10[MIR] Fix cyclic dependency of MIR formatterPeng Guo1-8/+8
2020-01-08Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders1-32/+25
2020-01-08Revert "[MIR] Target specific MIR formating and parsing"Nico Weber1-25/+32
2020-01-08[MIR] Target specific MIR formating and parsingPeng Guo1-32/+25
2020-01-08Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders1-25/+32
2020-01-08[MIR] Target specific MIR formating and parsingPeng Guo1-32/+25
2019-10-21[Alignment][NFC] Finish transition for `Loads`Guillaume Chatelet1-1/+2
2019-10-02[CodeGen] Remove unused MachineMemOperand::print wrappers (PR41772)Simon Pilgrim1-11/+0
2019-09-24MCRegisterInfo: Merge getLLVMRegNum and getLLVMRegNumFromEHPavel Labath1-5/+3
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-1/+1
2019-08-13GlobalISel: Change representation of shuffle masksMatt Arsenault1-0/+18
2019-08-06CodeGen: Migration to using RegisterMatt Arsenault1-6/+6
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-7/+7
2019-07-31SelectionDAG, MI, AArch64: Widen target flags fields/arguments from unsigned ...Peter Collingbourne1-3/+3
2019-06-24CodeGen: Introduce a class for registersMatt Arsenault1-1/+1
2019-06-14Fix not calling TargetCustom PSVs printerMatt Arsenault1-1/+1
2019-06-01[CodeGen] Fix hashing for MO_ExternalSymbol MachineOperands.Eli Friedman1-1/+1
2019-05-15[MachineOperand] Add a ChangeToGA methodNicolai Haehnle1-0/+13
2019-04-12Include what's used in a few cpp files - these were getting transitiveEric Christopher1-0/+1
2019-01-31GlobalISel: Fix creating MMOs with align 0Matt Arsenault1-1/+1
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-12-18[AArch64] - Return address signing dwarf supportLuke Cheeseman1-0/+5
2018-11-23Revert r347490 as it breaks address sanitizer buildsLuke Cheeseman1-5/+0
2018-11-23Revert r343341Luke Cheeseman1-0/+5
2018-10-30MachineOperand/MIParser: Do not print debug-use flag, infer itMatthias Braun1-2/+2
2018-10-25Fix in MachineOperand::printIRValueReference().Jonas Paulsson1-1/+2
2018-09-28Revert r343317Luke Cheeseman1-5/+0
2018-09-28Reapply changes reverted by r343235Luke Cheeseman1-0/+5
2018-09-27Revert r343192 as an ubsan build is currently failingLuke Cheeseman1-5/+0
2018-09-27Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman1-0/+5
2018-09-26Revert r343112 as CallFrameString API change has broken lldb buildsLuke Cheeseman1-5/+0
2018-09-26[AArch64] - Return address signing dwarf supportLuke Cheeseman1-0/+5
2018-09-26Revert r343089 "[AArch64] - Return address signing dwarf support"Hans Wennborg1-5/+0
2018-09-26[AArch64] - Return address signing dwarf supportLuke Cheeseman1-0/+5
2018-08-20Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek1-1/+6
2018-05-31[ADT] Make escaping fn conform to coding guidelinesJonas Devlieghere1-1/+1
2018-05-07[MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visi...Roman Tereshin1-1/+7
2018-04-30IWYU for llvm-config.h in llvm, additions.Nico Weber1-0/+1
2018-04-09Fix type mismatch between MachineMemOperand constructor and accessors. NFCDaniel Sanders1-1/+1
2018-03-30[MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi1-1/+9
2018-03-27[CodeGen] Fixed unreachable with -print-machineinstrs and custom pseudo sourc...Tim Renouf1-1/+6
2018-03-14[CodeGen] Use MIR syntax for MachineMemOperand printingFrancis Visoiu Mistrih1-103/+168
2018-02-23[MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry1-15/+15
2018-01-18[CodeGen][NFC] Rename IsVerbose to IsStandalone in Machine*::printFrancis Visoiu Mistrih1-3/+3
2018-01-18[CodeGen] Print RegClasses on MI in verbose modeFrancis Visoiu Mistrih1-3/+3
2018-01-16[CodeGen][NFC] Correct case for printSubRegIdxFrancis Visoiu Mistrih1-1/+1
2018-01-10[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi1-1/+1
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