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path: root/llvm/lib/CodeGen/MachineCSE.cpp
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2024-09-04[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)Christudasan Devadasan1-122/+162
2024-09-04[CodeGen][MachineCSE] Remove unused AA results(NFC) (#106604)Christudasan Devadasan1-5/+0
2024-08-29[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)Stephen Tozer1-1/+2
2024-07-12[CodeGen][NewPM] Port `machine-block-freq` to new pass manager (#98317)paperchalice1-3/+3
2024-07-12[CodeGen] Guard copy propagation in machine CSE against undefs (#97413)Vikram Hegde1-1/+1
2024-06-11[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result...paperchalice1-4/+4
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang1-1/+1
2023-12-03[llvm] Stop including vector (NFC)Kazu Hirata1-1/+0
2023-08-31Emit the CodeView `S_ARMSWITCHTABLE` debug symbol for jump tablesDaniel Paoliello1-1/+1
2023-08-25Revert "Emit the CodeView `S_ARMSWITCHTABLE` debug symbol for jump tables"Arthur Eubanks1-1/+1
2023-08-25Emit the CodeView `S_ARMSWITCHTABLE` debug symbol for jump tablesDaniel Paoliello1-1/+1
2023-08-07[MachineCSE] Add an option to override the profitability heuristicsJingu Kang1-0/+7
2023-06-01[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.Jay Foad1-8/+4
2023-04-17Fix uninitialized pointer members in CodeGenAkshay Khadse1-6/+6
2023-01-13[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFCCraig Topper1-10/+9
2022-11-14[MachineCSE] Allow CSE for instructions with ignorable operandsGuozhi Wei1-3/+6
2022-11-02[MachineCSE] Allow PRE of instructions that read physical registersJohn Brawn1-10/+22
2022-10-28Revert "[MachineCSE] Allow PRE of instructions that read physical registers"John Brawn1-15/+4
2022-10-27[MachineCSE] Allow PRE of instructions that read physical registersJohn Brawn1-4/+15
2022-09-16[MachineCSE] Add a threshold to avoid spending too much time in isProfitableT...Pengxuan Zheng1-3/+16
2022-08-31[MachineCSE] Use TargetInstrInfo::isAsCheapAsAMove in isPRECandidate.Craig Topper1-1/+1
2022-07-18CodeGen: Remove AliasAnalysis from regallocMatt Arsenault1-1/+1
2022-04-14MachineCSE: Report this requires SSAMatt Arsenault1-0/+5
2022-03-16Cleanup codegen includesserge-sans-paille1-1/+0
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-0/+1
2022-03-10Cleanup codegen includesserge-sans-paille1-1/+0
2021-10-30[MachineCSE] Use make_early_inc_range (NFC)Kazu Hirata1-48/+42
2021-05-05[MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent in...Michael Kitzan1-5/+27
2021-04-23[MachineCSE] Prevent CSE of non-local convergent instrsMichael Kitzan1-1/+5
2021-01-21[CodeGen] Use llvm::append_range (NFC)Kazu Hirata1-4/+2
2020-10-28[NFC] Use [MC]Register in CSE & LICMGaurav Jain1-17/+17
2020-09-26MachineCSE.cpp - use auto const& iterators in for-range loops to avoid copies...Simon Pilgrim1-2/+2
2020-09-21MachineCSE.cpp - use auto const& iterator in for-range loop to avoid copies. ...Simon Pilgrim1-2/+2
2020-07-06DomTree: Remove getChildren() accessorNicolai Hähnle1-5/+3
2020-04-06[MachineCSE] Don't carry the wrong location when hoistingDavide Italiano1-0/+7
2019-11-13Sink all InitializePasses.h includesReid Kleckner1-0/+1
2019-09-02[DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locationsJeremy Morse1-3/+5
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-9/+9
2019-08-07[MachineCSE][NFC] Use 'profitable' rather than 'beneficial' to name method.Kai Luo1-8/+8
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-13/+11
2019-07-19[MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.Kai Luo1-0/+25
2019-06-12[MIR] Skip hoisting to basic block which may throw exception or returnAnton Afanasyev1-0/+2
2019-06-09[MIR] Add simple PRE pass to MachineCSEAnton Afanasyev1-9/+118
2019-06-05Allow target to handle STRICT floating-point nodesUlrich Weigand1-1/+1
2019-05-27Revert r361356: "[MIR] Add simple PRE pass to MachineCSE"David L. Jones1-113/+9
2019-05-22[MIR] Add simple PRE pass to MachineCSEAnton Afanasyev1-9/+113
2019-05-03Revert "[MIR] Add simple PRE pass to MachineCSE"Anton Afanasyev1-117/+9
2019-05-03[MIR] Add simple PRE pass to MachineCSEAnton Afanasyev1-9/+117
2019-02-20[Codegen] Remove dead flags on Physical Defs in machine cseDavid Green1-19/+24
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
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