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2023-12-04[𝘀𝗽𝗿] changes introduced through rebaseusers/vitalybuka/spr/main.nfcasan-replace-a-few-if-sanitizer_apple-with-if-sanitizer_appleVitaly Buka4-0/+14
Created using spr 1.3.4 [skip ci]
2023-12-04[NFC][ASAN] Replace AsanInitIsRunning with TryAsanInitFromRtlVitaly Buka4-23/+30
Reviewers: zacklj89 Reviewed By: zacklj89 Pull Request: https://github.com/llvm/llvm-project/pull/74171
2023-12-04[libc] build with -Werror (#73966)Nick Desaulniers2-0/+12
A recent commit introduced warnings observable when building unit tests. If the unit tests don't fail when warnings are introduced into the build, then we might fail to notice them in the stream of output from check-libc. Link: https://github.com/llvm/llvm-project/pull/72763/files#r1410932348
2023-12-04[𝘀𝗽𝗿] changes introduced through rebaseVitaly Buka928-12379/+39971
Created using spr 1.3.4 [skip ci]
2023-12-04[libc] Add the missing math_extras.h include (#74259)Petr Hosek2-0/+2
math_extras.h is used in integer_utils.h when building for 32-bit platforms but the include is missing.
2023-12-04[NFC][ASAN] Move ENSURE_ASAN_INITED into AsanInitFromRtl (#74170)Vitaly Buka2-7/+6
2023-12-04[RISCV] Rework IDiv and FDiv pipes on SiFive7 (#73970)Michael Maitland2-2/+67
Set BufferSize=0 and remove Super pipes for these resources.
2023-12-04Use Address for CGBuilder's CreateAtomicRMW and CreateAtomicCmpXchg. (#74349)James Y Knight9-95/+198
Update all callers to pass through the Address. For the older builtins such as `__sync_*` and MSVC `_Interlocked*`, natural alignment of the atomic access is _assumed_. This change preserves that behavior. It will pass through greater-than-required alignments, however.
2023-12-04[libc][NFC] unify startup library's code style with the rest (#74041)Schrodinger ZHU Yifan5-47/+48
This PR unifies the startup library's code style with the rest of libc.
2023-12-04[sanitizer_symbolizer] RenderContextual elements for symbolizer markup.Andres Villegas7-1/+160
This is part of a stack of PRs to add support for symbolizer markup in linux. Render contextual symbolizer markup elements. For Fuchsia it is not necessary to emit any context given that Fuchsia's logging infrastructure already handles emitting it when necessary. For more information about contextual symbolizer markup elements: https://llvm.org/docs/SymbolizerMarkupFormat.html#contextual-elements Reviewers: PiJoules, petrhosek, vitalybuka Reviewed By: petrhosek, vitalybuka Pull Request: https://github.com/llvm/llvm-project/pull/73194
2023-12-04[lldb][NFC] Delete unreachable code and dead variable in OptionArgParserFelipe de Azevedo Piovezan1-36/+26
With the combination of an early return and removing an else-after-return, it becomes evident that there is unreachable code in the function being changed.
2023-12-04[lldb][NFC] Remove else after return in OptionArgParseFelipe de Azevedo Piovezan1-12/+9
This will enable us to prove that there is unreachable code in this function in a subsequent commit.
2023-12-04[lldb][NFC] Remove unnecessary std::string temporariesFelipe de Azevedo Piovezan1-5/+5
The existing code was taking three substrings from a regex match and converting to std::strings prior to using them. This may have been done to address null-termination concerns, but this is not the case: 1. `name` was being used to call `c_str()` and then implicitly converted back to a `StringRef` on the call to `ToAddress`. While the path `const char *` -> `StringRef` requires null-termination, we can simply use the original StringRef. 2. `str_offset` was being converted back to a StringRef in order to call a member method. Member methods can't handle non-null termination. 3. `sign` simply had it's 0-th element accessed.
2023-12-04XFailing test cases that fail on PowerPCKamau Bridgeman7-0/+7
These test cases fail when the libcxx and libcxxabi runtimes are built on Linux PowerPC. XFailing them until the issue is resolved.
2023-12-04[mlir][llvm] Fix attribute printer warning (NFC)(#74351)Tobias Gysi1-5/+4
This commit fixes a compilation warning caused by the printExpressionArg function that previously returned LogicalResult instead of void. The warning has been introduced by #73367.
2023-12-04[MLIR][NVVM]: Add cp.async.mbarrier.arrive Op (#74241)Durga3-0/+75
Add: * an Op for 'cp.async.mbarrier.arrive', targeting the nvvm_cp_async_mbarrier_arrive* family of intrinsics. * The 'noinc' intrinsic property is modelled as a default-valued-attr of type I1. * Test cases are added to verify the Op as well as the intrinsic lowering. Signed-off-by: Durgadoss R <durgadossr@nvidia.com>
2023-12-04[flang] IEEE_ARITHMETIC and IEEE_EXCEPTIONS intrinsic module procedures (#74138)vdonaldson32-208/+2804
Implement a selection of intrinsic module procedures that involve exceptions. - IEEE_GET_FLAG - IEEE_GET_HALTING_MODE - IEEE_GET_MODES - IEEE_GET_STATUS - IEEE_LOGB - [f23] IEEE_MAX, IEEE_MAX_MAG, IEEE_MAX_NUM, IEEE_MAX_NUM_MAG - [f23] IEEE_MIN, IEEE_MIN_MAG, IEEE_MIN_NUM, IEEE_MIN_NUM_MAG - IEEE_QUIET_EQ, IEEE_QUIET_GE, IEEE_QUIET_GT, - IEEE_QUIET_LE, IEEE_QUIET_LT, IEEE_QUIET_NE - IEEE_SET_FLAG - IEEE_SET_HALTING_MODE - IEEE_SET_MODES - IEEE_SET_STATUS - IEEE_SIGNALING_EQ, IEEE_SIGNALING_GE, IEEE_SIGNALING_GT, - IEEE_SIGNALING_LE, IEEE_SIGNALING_LT, IEEE_SIGNALING_NE - IEEE_SUPPORT_FLAG - IEEE_SUPPORT_HALTING
2023-12-04[SPIR-V] Add SPIRV-Tools for testing (#73044)Natalie Chouinard7-0/+140
Add spirv-dis (disassembler) and spirv-val (validator) from SPIRV-Tools as external dependencies for testing the SPIR-V backend. These tools are test dependencies only. SPIR-V backend tests now have a dependency on the spirv-dis and spirv-val targets when the `LLVM_INCLUDE_SPIRV_TOOLS_TESTS` cmake variable is set, which allows additional test files with the `REQUIRES: spirv-tools` constraint to run, along with additional `RUN: %if spirv-tools ...` lines in existing tests. All other SPIR-V backend tests will run normally when `LLVM_INCLUDE_SPIRV_TOOLS_TESTS` is not set. Several tests are included to show these tools' use, however more tests will be migrated and added later. * OpVariable_order.ll shows how spirv-val can catch bugs in the backend. * basic_int_types_spirvdis.ll shows how tests can be much shorter and more readable by FileChecking the spirv-dis output. * basic_int_types.ll shows how an additional RUN line can add validation to existing tests. RFC: https://discourse.llvm.org/t/rfc-add-a-test-dependency-on-spirv-tools/75135
2023-12-04[mlir][mesh] Add TableGen deffinitions of more collective ops (#73842)Boian Petkantchin3-0/+409
Add definitions for broadcast, gather, receive, reduce, scatter, send and shift.
2023-12-04[mlir][ArmSME] Remove ArmSMETypeConverter (and configure LLVM one instead) ↵Benjamin Maxwell8-39/+69
(#73639) This patch removes the ArmSMETypeConverter, and instead updates `populateArmSMEToLLVMConversionPatterns()` to add an ArmSME vector type conversion to the existing LLVMTypeConverter. This makes it easier to add these patterns to an existing `-to-llvm` lowering pass.
2023-12-04[mlir][vector] Make `TransposeOpLowering` configurable (#73915)Andrzej Warzyński2-16/+28
Following the discussion here: * https://github.com/llvm/llvm-project/pull/72105 this patch makes the `TransposeOpLowering` configurable so that one can select whether to favour `vector.shape_cast` over `vector.transpose`. As per the discussion in #72105, using `vector.shape_cast` is very beneficial and desirable when targeting `LLVM IR` (CPU lowering), but won't work when targeting `SPIR-V` today (GPU lowering). Hence the need for a mechanism to be able to disable/enable the pattern introduced in #72105. This patch proposes one such mechanism. While this should solve the problem that we are facing today, it's understood to be a temporary workaround. It should be removed once support for lowering `vector.shape_cast` to SPIR-V is added. Also, (once implemented) the following proposal might make this workaround redundant: * https://discourse.llvm.org/t/improving-handling-of-unit-dimensions-in-the-vector-dialect/
2023-12-04[flang] Remove GCC 7.2 workarounds (#73574)Brad Smith2-34/+6
The minimum GCC version was bumped from 7.1 to 7.4 so garbage collect the 7.2 workarounds. https://reviews.llvm.org/D156286
2023-12-04[bazel] Add missing dependency for 3a03da37a3c1e146ce7af1a1bbf8a2d3a0bf53dfBenjamin Kramer1-0/+1
2023-12-04Remove unused includes. NFC.Benjamin Kramer1-3/+0
2023-12-04[clang-tidy] readability-container-contains literal suffixes (#74215)Thomas Schenker3-2/+37
Before this PR, readability-container-contains fix-its did not handle integer literal suffixes correctly. It e.g. changed ``` MyMap.count(2) != 0U; ``` into ``` MyMap.contains(2)U; ``` With this PR, it correctly changes it to ``` MyMap.contains(2); ```
2023-12-04[analyzer] Let the checkers query upper and lower bounds on symbols (#74141)DonatNagyE6-14/+118
This commit extends the class `SValBuilder` with the methods `getMinValue()` and `getMaxValue()` to that work like `SValBuilder::getKnownValue()` but return the minimal/maximal possible value the `SVal` is not perfectly constrained. This extension of the ConstraintManager API is discussed at: https://discourse.llvm.org/t/expose-the-inferred-range-information-in-warning-messages/75192 As a simple proof-of-concept application of this new API, this commit extends a message from `core.BitwiseShift` with some range information that reports the assumptions of the analyzer. My main motivation for adding these methods is that I'll also want to use them in `ArrayBoundCheckerV2` to make the error messages less awkward, but I'm starting with this simpler and less important usecase because I want to avoid merge conflicts with my other commit https://github.com/llvm/llvm-project/pull/72107 which is currently under review. The testcase `too_large_right_operand_compound()` shows a situation where querying the range information does not work (and the extra information is not added to the error message). This also affects the debug utility `clang_analyzer_value()`, so the problem isn't in the fresh code. I'll do some investigations to resolve this, but I think that this commit is a step forward even with this limitation.
2023-12-04[Verifier] Check function attributes related to branch protection (NFC) (#70565)Momchil Velikov5-10/+53
2023-12-04[TargetInstrInfo] update INLINEASM memoperands once (#74135)Nick Desaulniers1-22/+21
In commit b05335989239 ("[X86InstrInfo] support memfold on spillable inline asm (#70832)"), I had a last minute fix to update the memoperands. I originally did this in the parent foldInlineAsmMemOperand call, updated the mir test via update_mir_test_checks.py, but then decided to move it to the child call of foldInlineAsmMemOperand. But I forgot to rerun update_mir_test_checks.py. That last minute change caused the same memoperand to be added twice when recursion occurred (for tied operands). I happened to get lucky that trailing content omitted from the CHECK line doesn't result in test failure. But rerunning update_mir_test_checks.py on the mir test added in that commit produces updated output. This is resulting in updates to the test that: 1. conflate additions to the test in child commits with simply updating the test as it should have been when first committed. 2. look wrong because the same memoperand is specified twice (we don't deduplicate memoperands when added). Example: INLINEASM ... :: (load (s32) from %stack.0) (load (s32) from %stack.0) Fix the bug, so that in child commits, we don't have additional unrelated test changes (which would be wrong anyways) from simply running update_mir_test_checks.py. Link: #20571
2023-12-04Fix #41439: Update the documentation with the correct information. (#69377)Da-Viper1-2/+11
Fixes #41439 The documentation is update to say it is allowed to have omitted parameter names if the variable is not used
2023-12-04[SystemZ] Handle index-only addresses in (dis)assemblerUlrich Weigand7-26/+49
Most addresses in SystemZ instructions take two registers, an index register and a base register. However, either of those can be omitted. If there is just a single register, this usually is taken as the base register - however, there are certain rare cases where you specifically want to use an index register but no base register. This is currently not handled consistently by the assembler / disassembler. Fix this by - always emitting a dummy 0 as base register for index- only addresses - correctly handle dummy 0 as indicating no base register when parsing an address This is compatible with current GNU binutils behavior.
2023-12-04[SystemZ] Fix __builtin_s390_vceq* inconsistencyUlrich Weigand3-184/+185
The __builtin_s390_vceq* family of builtins currently take signed arguments with clang, but unsigned with GCC. Update clang to match existing GCC precendent.
2023-12-04[SystemZ] Fix naming of vlrlr/vstrlr builtinsUlrich Weigand4-8/+8
The builtins that expand to the vlrl/vlrlr and vstrl/vstrlr instructions are currently named inconsistently between GCC and clang. Rename the clang versions to match GCC.
2023-12-04[SystemZ] Implement vector rotate in terms of funnel shiftUlrich Weigand13-208/+401
Clang currently implements a set of vector rotate builtins (__builtin_s390_verll*) in terms of platform-specific LLVM intrinsics. To simplify the IR (and allow for common code optimizations if applicable), this patch removes those LLVM intrinsics and implements the builtins in terms of the platform-independent funnel shift intrinsics instead. Also, fix the prototype of the __builtin_s390_verll* builtins for full compatibility with GCC.
2023-12-04[mlir][nvvm] Introduce `nvvm.fence.proxy` (#74057)Guray Ozen4-0/+90
This PR introduce `nvvm.fence.proxy` OP for the following cases: ``` nvvm.fence.proxy { kind = #nvvm.proxy_kind<alias>} nvvm.fence.proxy { kind = #nvvm.proxy_kind<async>} nvvm.fence.proxy { kind = #nvvm.proxy_kind<async.global>} nvvm.fence.proxy { kind = #nvvm.proxy_kind<async.shared>, space = #nvvm.shared_space<cta>} nvvm.fence.proxy { kind = #nvvm.proxy_kind<async.shared>, space = #nvvm.shared_space<cluster>} ```
2023-12-04[mlir][nvgpu] Add address space attribute converter in nvgpu-to-nvvm pass ↵Guray Ozen3-0/+44
(#74075) GPU dialect has `#gpu.address_space<workgroup>` for shared memory of NVGPU (address space =3). Howeverm when IR combine NVGPU and GPU dialect, `nvgpu-to-nvvm` pass fails due to missing attribute conversion. This PR adds `populateGpuMemorySpaceAttributeConversions` to nvgou-to-nvvm lowering, so we can use `#gpu.address_space<workgroup>` `nvgpu-to-nvvm` pass
2023-12-04[SystemZ] Auto-generate vec-intrinsics testsUlrich Weigand4-944/+1292
2023-12-04[VPlan] Sink cases where no truncate is needed in truncateMinimalBWs.Florian Hahn2-27/+107
MinBWs contains entries that specify the minimum required bitwidth. In some cases, the old and new bitwidths can be equal (see test case) and in those cases no truncations are needed, so skip those cases. Fixes #74307.
2023-12-04[AutoUpgrade] Simplify vclz upgrade (NFC)Nikita Popov1-10/+2
We can use Intrinsic::getDeclaration() here, we just have to pass the correct arguments. This function accepts only the mangled types, not all argument types.
2023-12-04[flang] (Re-)Enable alias tags pass by default (#74250)Tom Eccles8-21/+60
Enable by default for optimization levels higher than 0 (same behavior as clang). For simplicity, only forward the flag to the frontend driver when it contradicts what is implied by the optimization level. This was first landed in https://github.com/llvm/llvm-project/pull/73111 but was later reverted due to a performance regression. That regression was fixed by https://github.com/llvm/llvm-project/pull/74065.
2023-12-04[git] Add _LIBCPP_INLINE_VISIBILITY renaming to .git-blame-ignore-revs fileLouis Dionne1-0/+3
2023-12-04[libc++] Rename _LIBCPP_INLINE_VISIBILITY to _LIBCPP_HIDE_FROM_ABI (#74095)Louis Dionne234-5101/+5095
In preparation for running clang-format on the whole code base, we are also removing mentions of the legacy _LIBCPP_INLINE_VISIBILITY macro in favor of the newer _LIBCPP_HIDE_FROM_ABI. We're still leaving the definition of _LIBCPP_INLINE_VISIBILITY to avoid creating needless breakage in case some older patches are checked-in with mentions of the old macro. After we branch for LLVM 18, we can do another pass to clean up remaining uses of the macro that might have gotten introduced by mistake (if any) and remove the macro itself at the same time. This is just a minor convenience to smooth out the transition as much as possible. See https://discourse.llvm.org/t/rfc-clang-formatting-all-of-libc-once-and-for-all for the clang-format proposal.
2023-12-04[X86] Regenerate combine-or.llSimon Pilgrim1-19/+12
2023-12-04[CodeGen] Remove redundant ID in WinEHPrepareImpl (#74322)paperchalice1-1/+0
Fix ppc build bot
2023-12-04[mlir] Add support for DIGlobalVariable and DIGlobalVariableExpression (#73367)Justin Wilson18-27/+379
This PR introduces DIGlobalVariableAttr and DIGlobalVariableExpressionAttr so that ModuleTranslation can emit the required metadata needed for debug information about global variable. The translator implementation for debug metadata needed to be refactored in order to allow translation of nodes based on MDNode (DIGlobalVariableExpressionAttr and DIExpression) in addition to DINode-based nodes. A DIGlobalVariableExpressionAttr can now be passed to the GlobalOp operation directly and ModuleTranslation will create the respective DIGlobalVariable and DIGlobalVariableExpression nodes. The compile unit that DIGlobalVariable is expected to be configured with will be updated with the created DIGlobalVariableExpression.
2023-12-04[IndVarSimplify] Regenerate test checks (NFC)Nikita Popov1-112/+481
2023-12-04[gn build] Port bc8cff1d7fb2LLVM GN Syncbot1-0/+1
2023-12-04[clang-tidy] Add new modernize-use-starts-ends-with check (#72385)Nicolas van Kempen14-6/+374
Make a modernize version of abseil-string-find-startswith using the available C++20 `std::string::starts_with` and `std::string_view::starts_with`. Following up from https://github.com/llvm/llvm-project/pull/72283.
2023-12-04[AMDGPU][True16][GISel] Support v_add_f16 codegen. (#74122)Ivan Kosarev2-124/+456
2023-12-04[flang] Fix move-assign operator for struct IncrementLoopInfo (#74137)Krzysztof Parzyszek1-5/+5
2023-12-04 [clang][NFC] Refactor expected directives in C++ DRs 400-499 (#74311)Vlad Serebrennikov1-238/+421
This patch continues the work started with ea5b1ef016d020c37f903d6c7d4f623be975dab8. See that commit and its corresponding PR for details.