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2015-05-01Merging r227503:Tom Stellard4-12/+35
------------------------------------------------------------------------ r227503 | reid | 2015-01-29 17:33:00 -0500 (Thu, 29 Jan 2015) | 11 lines Update comments to use unreachable instead of llvm.trap, as implemented now win64: Call __chkstk through a register with the large code model Fixes half of PR18582. True dynamic allocas will still have a CALL64pcrel32 which will fail. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D7267 ------------------------------------------------------------------------ llvm-svn: 236302
2015-04-30Merging r231259:Tom Stellard4-3/+35
------------------------------------------------------------------------ r231259 | marek.olsak | 2015-03-04 12:33:45 -0500 (Wed, 04 Mar 2015) | 4 lines R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32 Required by OpenGL (ARB_gpu_shader5). ------------------------------------------------------------------------ llvm-svn: 236263
2015-04-30Merging r236099:Daniel Sanders4-16/+17
------------------------------------------------------------------------ r236099 | dsanders | 2015-04-29 13:28:58 +0100 (Wed, 29 Apr 2015) | 13 lines [mips] Correct 128-bit shifts on 64-bit targets. Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 ------------------------------------------------------------------------ llvm-svn: 236215
2015-04-29Correct syntax of getelementptr in regression test. NFCPawel Bylica2-13/+10
Bonus: unused variable removed. llvm-svn: 236116
2015-04-29Attempt #2: Fix ABI compatibility with 3.6.0 by moving new virtual function ↵Daniel Sanders1-6/+5
to end of subclass. NFC The previous attempt at fixing this only moved the problem to the subclass vtable. We can safely move the function into the subclass so attempt to fix it that way. llvm-svn: 236112
2015-04-29Merge r232176: ConstantFold: Fix big shift constant foldingPawel Bylica2-21/+81
Constant folding for shift IR instructions ignores all bits above 32 of second argument (shift amount). Because of that, some undef results are not recognized and APInt can raise an assert failure if second argument has more than 64 bits. Patch by Paweł Bylica! Differential Revision: http://reviews.llvm.org/D7701 llvm-svn: 236109
2015-04-29Merge r231984: Handle big index in getelementptr instructionPawel Bylica3-21/+92
CodeGen incorrectly ignores (assert from APInt) constant index bigger than 2^64 in getelementptr instruction. This is a test and fix for that. Patch by Paweł Bylica! Reviewed By: rnk Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits Differential Revision: http://reviews.llvm.org/D8219 llvm-svn: 236108
2015-04-29Fix ABI compatibility with 3.6.0 by moving new virtual function to end of ↵Daniel Sanders1-5/+6
class. NFC. llvm-svn: 236094
2015-04-29Merging r234891:Tom Stellard2-6/+38
------------------------------------------------------------------------ r234891 | thomas.stellard | 2015-04-14 10:36:45 -0400 (Tue, 14 Apr 2015) | 12 lines R600/SI: Fix verifier error caused by SIAnnotateControlFlow This pass will always try to insert llvm.SI.ifbreak intrinsics in the same block that its conditional value is computed in. This is a problem when conditions for breaks or continue are computed outside of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted outside of the loop. This patch fixes this problem by inserting the llvm.SI.ifbreak intrinsics in the loop header when the condition is computed outside the loop. ------------------------------------------------------------------------ llvm-svn: 236072
2015-04-29Merging r233080:Tom Stellard1-1/+16
------------------------------------------------------------------------ r233080 | marek.olsak | 2015-03-24 09:40:38 -0400 (Tue, 24 Mar 2015) | 4 lines R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI This is a candidate for stable. ------------------------------------------------------------------------ llvm-svn: 236071
2015-04-29Merging r233075:Tom Stellard5-8/+74
------------------------------------------------------------------------ r233075 | marek.olsak | 2015-03-24 09:40:08 -0400 (Tue, 24 Mar 2015) | 8 lines R600/SI: Expand fract to floor, then only select V_FRACT on CI V_FRACT is buggy on SI. R600-specific code is left intact. v2: drop the multiclass, use complex VOP3 patterns ------------------------------------------------------------------------ llvm-svn: 236070
2015-04-29Merging r232957:Tom Stellard2-3/+43
------------------------------------------------------------------------ r232957 | thomas.stellard | 2015-03-23 12:06:01 -0400 (Mon, 23 Mar 2015) | 5 lines R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr() This function assumed that SMRD instructions always have immediate offsets, which is not always the case. ------------------------------------------------------------------------ llvm-svn: 236069
2015-04-29Merging r234975:Tom Stellard2-11/+23
------------------------------------------------------------------------ r234975 | lhames | 2015-04-14 23:39:22 -0400 (Tue, 14 Apr 2015) | 5 lines [RuntimeDyld] Make sure we emit MachO __eh_frame and __gcc_except_tab sections, even if there are no references to them in the code. This allows exceptions thrown from JIT'd code to be caught by the JIT itself. ------------------------------------------------------------------------ llvm-svn: 236068
2015-04-29Merging r233410:Tom Stellard2-0/+111
------------------------------------------------------------------------ r233410 | ahmed.bougacha | 2015-03-27 16:35:49 -0400 (Fri, 27 Mar 2015) | 10 lines [CodeGen] Don't attempt a tail-call with a non-forwarded explicit sret. Tailcalls are only OK with forwarded sret pointers. With explicit sret, one approximation is to check that the pointer isn't an Instruction, as in that case it might point into some local memory (alloca). That's not OK with tailcalls. Explicit sret counterpart to r233409. Differential Revison: http://reviews.llvm.org/D8510 ------------------------------------------------------------------------ llvm-svn: 236067
2015-04-29Merging r233409:Tom Stellard2-0/+50
------------------------------------------------------------------------ r233409 | ahmed.bougacha | 2015-03-27 16:28:30 -0400 (Fri, 27 Mar 2015) | 7 lines [CodeGen] Don't attempt a tail-call with implicit sret. Tailcalls are only OK with forwarded sret pointers. With sret demotion, they're not, as we'd have a pointer into a soon-to-be-dead stack frame. Differential Revison: http://reviews.llvm.org/D8510 ------------------------------------------------------------------------ llvm-svn: 236066
2015-04-29Merging r232142:Tom Stellard2-4/+104
------------------------------------------------------------------------ r232142 | Hao.Liu | 2015-03-13 01:15:23 -0400 (Fri, 13 Mar 2015) | 9 lines [MachineCopyPropagation] Fix a bug causing incorrect removal for the instruction sequences as follows %Q5_Q6<def> = COPY %Q2_Q3 %D5<def> = %D3<def> = %D3<def> = COPY %D6 // Incorrectly removed in MachineCopyPropagation Using of %D3 results in incorrect result ... Reviewed in http://reviews.llvm.org/D8242 ------------------------------------------------------------------------ llvm-svn: 236065
2015-04-29MIPS: Fix test that uses 3.7 load syntaxTom Stellard1-19/+19
This was broken by r235973. llvm-svn: 236064
2015-04-28Merging r232797:Tom Stellard1-4/+4
------------------------------------------------------------------------ r232797 | thomas.stellard | 2015-03-19 23:12:42 -0400 (Thu, 19 Mar 2015) | 2 lines R600/SI: Add missing CHECK-LABEL lines to a test ------------------------------------------------------------------------ llvm-svn: 236041
2015-04-28Merging r232386:Tom Stellard2-0/+25
------------------------------------------------------------------------ r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines R600/SI: don't try min3/max3/med3 with f64 There are no opcodes for this. This also adds a test case. v2: make test more robust Patch by: Grigori Goronzy ------------------------------------------------------------------------ llvm-svn: 236040
2015-04-28Merging r231662:Tom Stellard1-2/+2
------------------------------------------------------------------------ r231662 | thomas.stellard | 2015-03-09 12:03:39 -0400 (Mon, 09 Mar 2015) | 2 lines R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64 ------------------------------------------------------------------------ llvm-svn: 236039
2015-04-28Merging r231659:Tom Stellard7-6/+51
------------------------------------------------------------------------ r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines R600/SI: Limit SGPRs to 80 on Tonga and Iceland This is a candidate for stable. ------------------------------------------------------------------------ llvm-svn: 236038
2015-04-28Merging r231658:Tom Stellard2-12/+24
------------------------------------------------------------------------ r231658 | marek.olsak | 2015-03-09 11:48:00 -0400 (Mon, 09 Mar 2015) | 2 lines R600/SI: Fix getNumSGPRsAllowed for VI ------------------------------------------------------------------------ llvm-svn: 236037
2015-04-28Merging r230147:Tom Stellard1-1/+21
------------------------------------------------------------------------ r230147 | Matthew.Arsenault | 2015-02-21 16:29:04 -0500 (Sat, 21 Feb 2015) | 2 lines R600/SI: Don't crash when getting immediate operand size ------------------------------------------------------------------------ llvm-svn: 236022
2015-04-28Merging r230146:Tom Stellard4-2/+40
------------------------------------------------------------------------ r230146 | Matthew.Arsenault | 2015-02-21 16:29:00 -0500 (Sat, 21 Feb 2015) | 2 lines R600/SI: Fix mad*k definitions ------------------------------------------------------------------------ llvm-svn: 236021
2015-04-28Merging r229752:Tom Stellard2-11/+10
------------------------------------------------------------------------ r229752 | marek.olsak | 2015-02-18 17:12:45 -0500 (Wed, 18 Feb 2015) | 10 lines R600/SI: Fix READLANE and WRITELANE lane select for VI VOP2 declares vsrc1, but VOP3 declares src1. We can't use the same "ins" if the operands have different names in VOP2 and VOP3 encodings. This fixes a hang in geometry shaders which spill M0 on VI. (BTW it doesn't look like M0 needs spilling and the spilling seems duplicated 3 times) ------------------------------------------------------------------------ llvm-svn: 236020
2015-04-28Merging r229751:Tom Stellard1-2/+3
------------------------------------------------------------------------ r229751 | marek.olsak | 2015-02-18 17:12:41 -0500 (Wed, 18 Feb 2015) | 2 lines R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C ------------------------------------------------------------------------ llvm-svn: 236019
2015-04-28Merging r229750:Tom Stellard1-25/+0
------------------------------------------------------------------------ r229750 | marek.olsak | 2015-02-18 17:12:37 -0500 (Wed, 18 Feb 2015) | 4 lines R600/SI: Remove explicit VOP operand checking This should be handled by the OperandType checking. ------------------------------------------------------------------------ llvm-svn: 236018
2015-04-28Merging r229507:Tom Stellard2-4/+52
------------------------------------------------------------------------ r229507 | thomas.stellard | 2015-02-17 11:36:00 -0500 (Tue, 17 Feb 2015) | 2 lines R600/SI: Extend private extload pattern to include zext loads ------------------------------------------------------------------------ llvm-svn: 236017
2015-04-28Merging r229239:Tom Stellard10-43/+184
------------------------------------------------------------------------ r229239 | Matthew.Arsenault | 2015-02-13 23:30:08 -0500 (Fri, 13 Feb 2015) | 4 lines R600/SI: Implement correct f64 fdiv This version passes the OpenCL conformance test. ------------------------------------------------------------------------ llvm-svn: 236016
2015-04-28Merging r232943:Daniel Sanders6-4/+235
------------------------------------------------------------------------ r232943 | petarj | 2015-03-23 12:28:13 +0000 (Mon, 23 Mar 2015) | 10 lines Fix sign extension for MIPS64 in makeLibCall function Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all 32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign extended. This fixes test "MultiSource/Applications/oggenc/". Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D7791 ------------------------------------------------------------------------ llvm-svn: 235973
2015-04-28Merging r228765:Daniel Sanders2-1/+16
------------------------------------------------------------------------ r228765 | petarj | 2015-02-10 23:30:14 +0000 (Tue, 10 Feb 2015) | 12 lines Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP function The isSigned argument of makeLibCall function was hard-coded to false (unsigned). This caused zero extension on MIPS64 soft float. As the result SingleSource/Benchmarks/Stanford/FloatMM test and SingleSource/UnitTests/2005-07-17-INT-To-FP test failed. The solution was to use the proper argument. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D7292 ------------------------------------------------------------------------ llvm-svn: 235972
2015-04-27Merging r231237:Daniel Sanders1-4/+2
------------------------------------------------------------------------ r231237 | vkalintiris | 2015-03-04 12:10:18 +0000 (Wed, 04 Mar 2015) | 6 lines [mips] Specify the correct value type when combining a CMovFP node. This commit fixes a bug introduced in r230956 where we were creating CMovFP_{T,F} nodes with multiple return value types (one for each operand). With this change the return value type of the new node is the same as the value type of the True/False operands of the original node. ------------------------------------------------------------------------ llvm-svn: 235888
2015-04-27Merging r230956:Daniel Sanders2-175/+159
------------------------------------------------------------------------ r230956 | vkalintiris | 2015-03-02 12:47:32 +0000 (Mon, 02 Mar 2015) | 10 lines [mips] Optimize conditional moves where RHS is zero. Summary: When the RHS of a conditional move node is zero, we can utilize the $zero register by inverting the conditional move instruction and by swapping the order of its True/False operands. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7945 ------------------------------------------------------------------------ llvm-svn: 235886
2015-04-27Merging r230500:Daniel Sanders12-86/+70
------------------------------------------------------------------------ r230500 | vmedic | 2015-02-25 15:24:37 +0000 (Wed, 25 Feb 2015) | 1 line [MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files. ------------------------------------------------------------------------ llvm-svn: 235885
2015-04-27Merging r228403:Daniel Sanders1-8/+4
------------------------------------------------------------------------ r228403 | dsanders | 2015-02-06 16:37:30 +0000 (Fri, 06 Feb 2015) | 2 lines [mips] Fix FileCheck prefixes with whitespace between 'CHECK' and ':' ------------------------------------------------------------------------ llvm-svn: 235884
2015-04-27Merging r233904:Daniel Sanders3-0/+26
------------------------------------------------------------------------ r233904 | vkalintiris | 2015-04-02 11:14:54 +0100 (Thu, 02 Apr 2015) | 9 lines [mips] Make sure that we don't adjust the stack pointer by zero amount. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8638 ------------------------------------------------------------------------ llvm-svn: 235883
2015-04-27Merging r232382:Daniel Sanders2-1/+81
------------------------------------------------------------------------ r232382 | petarj | 2015-03-16 15:01:09 +0000 (Mon, 16 Mar 2015) | 13 lines [MIPS] Fix justify error for small structures Fix justify error for small structures bigger than 32 bits in fixed arguments for MIPS64 big endian. There was a problem when small structures are passed as fixed arguments. The structures that are bigger than 32 bits but smaller than 64 bits were not left justified properly on MIPS64 big endian. This is fixed by shifting the value to make it left justified when appropriate. Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D8174 ------------------------------------------------------------------------ llvm-svn: 235879
2015-04-27Merging r230748:Daniel Sanders1-6/+6
------------------------------------------------------------------------ r230748 | tomatabacu | 2015-02-27 10:44:02 +0000 (Fri, 27 Feb 2015) | 11 lines [mips] Remove redundant periods from -mattr=help descriptions for MIPS. Summary: Also fixes an infringement of the 80-column limit rule. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7910 ------------------------------------------------------------------------ llvm-svn: 235876
2015-04-27Merging r230742:Daniel Sanders2-2/+35
------------------------------------------------------------------------ r230742 | vkalintiris | 2015-02-27 09:01:39 +0000 (Fri, 27 Feb 2015) | 12 lines [mips] Account for constant-zero operands in ADDE nodes. Summary: We identify the cases where the operand to an ADDE node is a constant zero. In such cases, we can avoid generating an extra ADDu instruction disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r). Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7906 ------------------------------------------------------------------------ llvm-svn: 235874
2015-04-27Merging r230657:Daniel Sanders4-0/+596
------------------------------------------------------------------------ r230657 | petarj | 2015-02-26 18:35:15 +0000 (Thu, 26 Feb 2015) | 13 lines Fix justify error for small structures in varargs for MIPS64BE There was a problem when passing structures as variable arguments. The structures smaller than 64 bit were not left justified on MIPS64 big endian. This is now fixed by shifting the value to make it left- justified when appropriate. This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608 Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D7881 ------------------------------------------------------------------------ llvm-svn: 235872
2015-04-27Merging r230235:Daniel Sanders3-5/+151
------------------------------------------------------------------------ r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 ------------------------------------------------------------------------ llvm-svn: 235870
2015-04-27Merging r229675:Daniel Sanders4-13/+11
------------------------------------------------------------------------ r229675 | vkalintiris | 2015-02-18 14:57:05 +0000 (Wed, 18 Feb 2015) | 7 lines [mips] Avoid redundant sign extension of the result of binary bitwise instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7581 ------------------------------------------------------------------------ llvm-svn: 235869
2015-04-27Merging r227430:Daniel Sanders8-7/+31
------------------------------------------------------------------------ r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. ------------------------------------------------------------------------ llvm-svn: 235864
2015-04-27Merging r227084:Daniel Sanders7-5/+11
------------------------------------------------------------------------ r227084 | vmedic | 2015-01-26 10:33:43 +0000 (Mon, 26 Jan 2015) | 1 line When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions. ------------------------------------------------------------------------ llvm-svn: 235859
2015-04-27Merging r227269:Daniel Sanders1-13/+2
------------------------------------------------------------------------ r227269 | petarj | 2015-01-27 23:30:18 +0000 (Tue, 27 Jan 2015) | 7 lines [mips] Use __clear_cache builtin instead of cacheflush() Use __clear_cache builtin instead of cacheflush() in Unix Memory::InvalidateInstructionCache(). Differential Revision: http://reviews.llvm.org/D7198 ------------------------------------------------------------------------ llvm-svn: 235858
2015-04-27Merging r226905:Daniel Sanders2-39/+50
------------------------------------------------------------------------ r226905 | tomatabacu | 2015-01-23 10:40:19 +0000 (Fri, 23 Jan 2015) | 18 lines [mips] Add new error message and improve testing for parsing the .module directive. Summary: We used to silently ignore any empty .module's and we used to give an error saying that we found an "unexpected token at start of statement" when the value of the option wasn't an identifier (e.g. if it was a number). We now give an error saying that we "expected .module option identifier" in both of those cases. I also fixed the other tests in mips-abi-bad.s, which all seemed to be broken. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7095 ------------------------------------------------------------------------ llvm-svn: 235856
2015-04-27Merging r226652:Daniel Sanders8-8/+39
------------------------------------------------------------------------ r226652 | vmedic | 2015-01-21 10:47:36 +0000 (Wed, 21 Jan 2015) | 1 line [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. ------------------------------------------------------------------------ llvm-svn: 235855
2015-04-27Merging r226409:Daniel Sanders5-301/+301
------------------------------------------------------------------------ r226409 | dsanders | 2015-01-18 18:43:10 +0000 (Sun, 18 Jan 2015) | 2 lines [mips] 'CHECK :' is not a valid check directive. Fixed. ------------------------------------------------------------------------ llvm-svn: 235850
2015-04-27Merging r226408:Daniel Sanders28-3854/+3854
------------------------------------------------------------------------ r226408 | dsanders | 2015-01-18 18:38:36 +0000 (Sun, 18 Jan 2015) | 9 lines [mips] Make whitespace in disassembler tests more consistent. NFC. The tests for the ISA's should now be approximately diffable. That is, the output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines for instructions that were added/removed to/from MIPS-I by MIPS-II. This doesn't work perfectly at the moment due to ordering differences but it should be close. ------------------------------------------------------------------------ llvm-svn: 235849
2015-04-27Merging r226407:Daniel Sanders15-1523/+0
------------------------------------------------------------------------ r226407 | dsanders | 2015-01-18 18:21:19 +0000 (Sun, 18 Jan 2015) | 3 lines [mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC. ------------------------------------------------------------------------ llvm-svn: 235848
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