diff options
Diffstat (limited to 'llvm/test/Transforms')
7 files changed, 364 insertions, 7 deletions
diff --git a/llvm/test/Transforms/ConstraintElimination/sub-nuw.ll b/llvm/test/Transforms/ConstraintElimination/sub-nuw.ll index 0d90bc2..5ae559d 100644 --- a/llvm/test/Transforms/ConstraintElimination/sub-nuw.ll +++ b/llvm/test/Transforms/ConstraintElimination/sub-nuw.ll @@ -316,12 +316,13 @@ define i1 @sub_nuw_neg_i16(i16 %a) { ; CHECK-LABEL: @sub_nuw_neg_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[NEG2:%.*]] = sub nuw i16 [[A:%.*]], -305 -; CHECK-NEXT: br i1 false, label [[EXIT_1:%.*]], label [[EXIT_2:%.*]] +; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i16 0, [[NEG2]] +; CHECK-NEXT: br i1 [[C_1]], label [[EXIT_1:%.*]], label [[EXIT_2:%.*]] ; CHECK: exit.1: -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: [[C_2:%.*]] = icmp ugt i16 [[A]], 0 +; CHECK-NEXT: ret i1 [[C_2]] ; CHECK: exit.2: -; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i16 [[A]], 0 -; CHECK-NEXT: ret i1 [[C_3]] +; CHECK-NEXT: ret i1 true ; entry: %neg2 = sub nuw i16 %a, -305 @@ -379,3 +380,117 @@ entry: %c = icmp ugt i64 %neg2, 0 ret i1 %c } + +define i1 @pr76713(i16 %i1, i16 %i3) { +; CHECK-LABEL: @pr76713( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[C1:%.*]] = icmp ult i16 [[I1:%.*]], -1 +; CHECK-NEXT: [[C2:%.*]] = icmp uge i16 [[I1]], -3 +; CHECK-NEXT: [[C3:%.*]] = icmp ult i16 [[I3:%.*]], 2 +; CHECK-NEXT: [[AND:%.*]] = and i1 [[C1]], [[C2]] +; CHECK-NEXT: [[AND_2:%.*]] = and i1 [[AND]], [[C3]] +; CHECK-NEXT: br i1 [[AND]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i16 [[I1]], -3 +; CHECK-NEXT: [[ARRAYIDX_IDX:%.*]] = mul nuw nsw i16 [[I3]], 4 +; CHECK-NEXT: [[I6:%.*]] = add nuw nsw i16 [[ARRAYIDX_IDX]], [[SUB]] +; CHECK-NEXT: [[C4:%.*]] = icmp ult i16 12, [[I6]] +; CHECK-NEXT: ret i1 [[C4]] +; CHECK: else: +; CHECK-NEXT: ret i1 false +; +entry: + %c1 = icmp ult i16 %i1, -1 + %c2 = icmp uge i16 %i1, -3 + %c3 = icmp ult i16 %i3, 2 + %and = and i1 %c1, %c2 + %and.2 = and i1 %and, %c3 + br i1 %and, label %then, label %else + +then: + %sub = sub nuw nsw i16 %i1, -3 + %arrayidx.idx = mul nuw nsw i16 %i3, 4 + %i6 = add nuw nsw i16 %arrayidx.idx, %sub + %c4 = icmp ult i16 12, %i6 + ret i1 %c4 + +else: + ret i1 0 +} + +define void @sub_nuw_chained_positive_constants(i16 %a) { +; CHECK-LABEL: @sub_nuw_chained_positive_constants( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SUB1:%.*]] = sub nuw i16 [[A:%.*]], 10 +; CHECK-NEXT: [[SUB2:%.*]] = sub nuw i16 [[SUB1]], 20 +; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i16 [[SUB2]], 90 +; CHECK-NEXT: br i1 [[C_1]], label [[EXIT_1:%.*]], label [[EXIT_2:%.*]] +; CHECK: exit.1: +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i16 [[A]], 121 +; CHECK-NEXT: call void @use(i1 [[C_3]]) +; CHECK-NEXT: ret void +; CHECK: exit.2: +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: ret void +; +entry: + %sub1 = sub nuw i16 %a, 10 + %sub2 = sub nuw i16 %sub1, 20 + %c.1 = icmp ugt i16 %sub2, 90 + br i1 %c.1, label %exit.1, label %exit.2 + +exit.1: + %c.2 = icmp ugt i16 %a, 120 + call void @use(i1 %c.2) + %c.3 = icmp ugt i16 %a, 121 + call void @use(i1 %c.3) + ret void + +exit.2: + %c.4 = icmp ugt i16 %a, 120 + call void @use(i1 %c.4) + %c.5 = icmp ugt i16 %a, 121 + call void @use(i1 %c.5) + ret void +} + +define void @sub_nuw_chained_negative_constants(i8 %a) { +; CHECK-LABEL: @sub_nuw_chained_negative_constants( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SUB1:%.*]] = sub nuw i8 [[A:%.*]], 10 +; CHECK-NEXT: [[SUB2:%.*]] = sub nuw i8 [[SUB1]], -126 +; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i8 [[SUB2]], 20 +; CHECK-NEXT: br i1 [[C_1]], label [[EXIT_1:%.*]], label [[EXIT_2:%.*]] +; CHECK: exit.1: +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i8 [[A]], -95 +; CHECK-NEXT: call void @use(i1 [[C_3]]) +; CHECK-NEXT: ret void +; CHECK: exit.2: +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: ret void +; +entry: + %sub1 = sub nuw i8 %a, 10 + %sub2 = sub nuw i8 %sub1, 130 + %c.1 = icmp ugt i8 %sub2, 20 + br i1 %c.1, label %exit.1, label %exit.2 + +exit.1: + %c.2 = icmp ugt i8 %a, 160 + call void @use(i1 %c.2) + %c.3 = icmp ugt i8 %a, 161 + call void @use(i1 %c.3) + ret void + + +exit.2: + %c.4 = icmp ugt i8 %a, 160 + call void @use(i1 %c.4) + %c.5 = icmp ugt i8 %a, 161 + call void @use(i1 %c.5) + ret void +} diff --git a/llvm/test/Transforms/InstCombine/and-xor-merge.ll b/llvm/test/Transforms/InstCombine/and-xor-merge.ll index 5433364..e6df4e3 100644 --- a/llvm/test/Transforms/InstCombine/and-xor-merge.ll +++ b/llvm/test/Transforms/InstCombine/and-xor-merge.ll @@ -40,3 +40,42 @@ define i32 @PR38781(i32 %a, i32 %b) { %and = and i32 %b.lobit.not, %a.lobit.not ret i32 %and } + +; (a ^ 4) & (a ^ ~4) -> 0 +define i32 @PR75692_1(i32 %x) { +; CHECK-LABEL: @PR75692_1 +; CHECK-NEXT: ret i32 0 +; + %t2 = xor i32 %x, 4 + %t3 = xor i32 %x, -5 + %t4 = and i32 %t2, %t3 + ret i32 %t4 +} + +; (a ^ 4) & (a ^ 3) is not zero +define i32 @PR75692_2(i32 %x) { +; CHECK-LABEL: @PR75692_2 +; CHECK-NEXT: %t2 = xor i32 %x, 4 +; CHECK-NEXT: %t3 = xor i32 %x, -4 +; CHECK-NEXT: %t4 = and i32 %t2, %t3 +; CHECK-NEXT: ret i32 %t4 +; + %t2 = xor i32 %x, 4 + %t3 = xor i32 %x, -4 + %t4 = and i32 %t2, %t3 + ret i32 %t4 +} + +; (a ^ 4) & (b ^ ~4) is not zero, since a != b is possible +define i32 @PR75692_3(i32 %x, i32 %y) { +; CHECK-LABEL: @PR75692_3 +; CHECK-NEXT: %t2 = xor i32 %x, 4 +; CHECK-NEXT: %t3 = xor i32 %y, -5 +; CHECK-NEXT: %t4 = and i32 %t2, %t3 +; CHECK-NEXT: ret i32 %t4 +; + %t2 = xor i32 %x, 4 + %t3 = xor i32 %y, -5 + %t4 = and i32 %t2, %t3 + ret i32 %t4 +} diff --git a/llvm/test/Transforms/InstCombine/or-xor.ll b/llvm/test/Transforms/InstCombine/or-xor.ll index 1d35332..361aab6 100644 --- a/llvm/test/Transforms/InstCombine/or-xor.ll +++ b/llvm/test/Transforms/InstCombine/or-xor.ll @@ -1055,3 +1055,42 @@ define i8 @or_nand_xor_common_op_commute3_use3(i8 %x, i8 %y, i8 %z) { %r = or i8 %xor, %nand ret i8 %r } + +; (a ^ 4) & (a ^ ~4) -> -1 +define i32 @PR75692_1(i32 %x) { +; CHECK-LABEL: @PR75692_1( +; CHECK-NEXT: ret i32 -1 +; + %t2 = xor i32 %x, 4 + %t3 = xor i32 %x, -5 + %t4 = or i32 %t2, %t3 + ret i32 %t4 +} + +; (a ^ 4) & (a ^ 3) is not -1 +define i32 @PR75692_2(i32 %x) { +; CHECK-LABEL: @PR75692_2 +; CHECK-NEXT: %t2 = xor i32 %x, 4 +; CHECK-NEXT: %t3 = xor i32 %x, -4 +; CHECK-NEXT: %t4 = or i32 %t2, %t3 +; CHECK-NEXT: ret i32 %t4 +; + %t2 = xor i32 %x, 4 + %t3 = xor i32 %x, -4 + %t4 = or i32 %t2, %t3 + ret i32 %t4 +} + +; (a ^ 4) & (b ^ ~4) is not -1, since a != b is possible +define i32 @PR75692_3(i32 %x, i32 %y) { +; CHECK-LABEL: @PR75692_3 +; CHECK-NEXT: %t2 = xor i32 %x, 4 +; CHECK-NEXT: %t3 = xor i32 %y, -5 +; CHECK-NEXT: %t4 = or i32 %t2, %t3 +; CHECK-NEXT: ret i32 %t4 +; + %t2 = xor i32 %x, 4 + %t3 = xor i32 %y, -5 + %t4 = or i32 %t2, %t3 + ret i32 %t4 +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll index 3bccfac..b762c3a 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll @@ -31,3 +31,30 @@ loop: %i4 = extractelement <2 x float> %ins1, i64 0 br label %loop } + +define void @test1() { +; CHECK-LABEL: define void @test1() { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x float> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x float> zeroinitializer, [[TMP0]] +; CHECK-NEXT: [[TMP2]] = select <2 x i1> zeroinitializer, <2 x float> [[TMP1]], <2 x float> zeroinitializer +; CHECK-NEXT: br label [[LOOP]] +; +entry: + br label %loop + +loop: + %ph0 = phi float [ 0.000000e+00, %entry ], [ %i4, %loop ] + %ph1 = phi float [ 0.000000e+00, %entry ], [ %i5, %loop ] + %i = fadd float 0.000000e+00, %ph0 + %i1 = fadd float 0.000000e+00, %ph1 + %i2 = select i1 false, float %i, float 0.000000e+00 + %i3 = select i1 false, float %i1, float 0.000000e+00 + %ins0 = insertelement <2 x float> zeroinitializer, float %i2, i64 0 + %ins1 = insertelement <2 x float> %ins0, float %i3, i64 1 + %i4 = extractelement <2 x float> %ins1, i64 0 + %i5 = extractelement <2 x float> %ins1, i64 1 + br label %loop +} diff --git a/llvm/test/Transforms/SimplifyCFG/switch-dead-default-lookup-table.ll b/llvm/test/Transforms/SimplifyCFG/switch-dead-default-lookup-table.ll new file mode 100644 index 0000000..bead0dc --- /dev/null +++ b/llvm/test/Transforms/SimplifyCFG/switch-dead-default-lookup-table.ll @@ -0,0 +1,61 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt %s -S -passes='simplifycfg<switch-to-lookup>' -simplifycfg-require-and-preserve-domtree=1 -switch-range-to-icmp | FileCheck %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + +define i64 @test_1(i64 %0) { +; CHECK-LABEL: define i64 @test_1( +; CHECK-SAME: i64 [[TMP0:%.*]]) { +; CHECK-NEXT: switch.lookup: +; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[TMP0]], 4 +; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [4 x i64], ptr @switch.table.test_1, i32 0, i64 [[TMP1]] +; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i64, ptr [[SWITCH_GEP]], align 8 +; CHECK-NEXT: ret i64 [[SWITCH_LOAD]] +; + %2 = urem i64 %0, 4 + switch i64 %2, label %5 [ + i64 1, label %3 + i64 2, label %3 + i64 3, label %4 + ] + +3: + br label %5 + +4: + br label %5 + +5: + %.0 = phi i64 [ 2, %4 ], [ 1, %3 ], [ 0, %1 ] + ret i64 %.0 +} + + +define i64 @test_2(i64 %0) { +; CHECK-LABEL: define i64 @test_2( +; CHECK-SAME: i64 [[TMP0:%.*]]) { +; CHECK-NEXT: switch.lookup: +; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[TMP0]], 4 +; CHECK-NEXT: ret i64 [[TMP1]] +; + %2 = urem i64 %0, 4 + switch i64 %2, label %6 [ + i64 1, label %3 + i64 2, label %4 + i64 3, label %5 + ] + +3: + br label %6 + +4: + br label %6 + +5: + br label %6 + +6: + %.0 = phi i64 [ 0, %1 ], [ 1, %3 ], [ 2, %4 ], [ 3, %5 ] + ret i64 %.0 +} + diff --git a/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll b/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll index 7c0d5e4..e30a535 100644 --- a/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll +++ b/llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll @@ -79,15 +79,15 @@ default: ret void } -; This one is a negative test - we know the value of the default, -; but that's about it +; We can replace the default branch with case 3 since it is the only case that is missing. define void @test3(i2 %a) { ; CHECK-LABEL: define void @test3( ; CHECK-SAME: i2 [[A:%.*]]) { -; CHECK-NEXT: switch i2 [[A]], label [[DEFAULT:%.*]] [ +; CHECK-NEXT: switch i2 [[A]], label [[DOTUNREACHABLEDEFAULT:%.*]] [ ; CHECK-NEXT: i2 0, label [[CASE0:%.*]] ; CHECK-NEXT: i2 1, label [[CASE1:%.*]] ; CHECK-NEXT: i2 -2, label [[CASE2:%.*]] +; CHECK-NEXT: i2 -1, label [[DEFAULT:%.*]] ; CHECK-NEXT: ] ; CHECK: common.ret: ; CHECK-NEXT: ret void @@ -100,6 +100,8 @@ define void @test3(i2 %a) { ; CHECK: case2: ; CHECK-NEXT: call void @foo(i32 2) ; CHECK-NEXT: br label [[COMMON_RET]] +; CHECK: .unreachabledefault: +; CHECK-NEXT: unreachable ; CHECK: default: ; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: br label [[COMMON_RET]] @@ -122,6 +124,50 @@ default: ret void } +define void @test3_prof(i2 %a) { +; CHECK-LABEL: define void @test3_prof( +; CHECK-SAME: i2 [[A:%.*]]) { +; CHECK-NEXT: switch i2 [[A]], label [[DOTUNREACHABLEDEFAULT:%.*]] [ +; CHECK-NEXT: i2 0, label [[CASE0:%.*]] +; CHECK-NEXT: i2 1, label [[CASE1:%.*]] +; CHECK-NEXT: i2 -2, label [[CASE2:%.*]] +; CHECK-NEXT: i2 -1, label [[DEFAULT:%.*]] +; CHECK-NEXT: ], !prof [[PROF0:![0-9]+]] +; CHECK: common.ret: +; CHECK-NEXT: ret void +; CHECK: case0: +; CHECK-NEXT: call void @foo(i32 0) +; CHECK-NEXT: br label [[COMMON_RET:%.*]] +; CHECK: case1: +; CHECK-NEXT: call void @foo(i32 1) +; CHECK-NEXT: br label [[COMMON_RET]] +; CHECK: case2: +; CHECK-NEXT: call void @foo(i32 2) +; CHECK-NEXT: br label [[COMMON_RET]] +; CHECK: .unreachabledefault: +; CHECK-NEXT: unreachable +; CHECK: default: +; CHECK-NEXT: call void @foo(i32 3) +; CHECK-NEXT: br label [[COMMON_RET]] +; + switch i2 %a, label %default [i2 0, label %case0 + i2 1, label %case1 + i2 2, label %case2], !prof !0 + +case0: + call void @foo(i32 0) + ret void +case1: + call void @foo(i32 1) + ret void +case2: + call void @foo(i32 2) + ret void +default: + call void @foo(i32 3) + ret void +} + ; Negative test - check for possible overflow when computing ; number of possible cases. define void @test4(i128 %a) { @@ -267,3 +313,7 @@ default: declare void @llvm.assume(i1) +!0 = !{!"branch_weights", i32 8, i32 4, i32 2, i32 1} +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 0, i32 4, i32 2, i32 1, i32 8} +;. diff --git a/llvm/test/Transforms/Util/add-TLI-mappings.ll b/llvm/test/Transforms/Util/add-TLI-mappings.ll index a407986..67ca00b 100644 --- a/llvm/test/Transforms/Util/add-TLI-mappings.ll +++ b/llvm/test/Transforms/Util/add-TLI-mappings.ll @@ -65,6 +65,32 @@ define float @call_llvm.log10.f32(float %in) { } declare float @llvm.log10.f32(float) #0 + +; SVML: declare <2 x double> @__svml_sin2(<2 x double>) +; SVML: declare <4 x double> @__svml_sin4(<4 x double>) +; SVML: declare <8 x double> @__svml_sin8(<8 x double>) +; SVML: declare <4 x float> @__svml_log10f4(<4 x float>) +; SVML: declare <8 x float> @__svml_log10f8(<8 x float>) +; SVML: declare <16 x float> @__svml_log10f16(<16 x float>) + +; MASSV: declare <2 x double> @__sind2(<2 x double>) +; MASSV: declare <4 x float> @__log10f4(<4 x float>) + +; LIBMVEC-X86: declare <2 x double> @_ZGVbN2v_sin(<2 x double>) +; LIBMVEC-X86: declare <4 x double> @_ZGVdN4v_sin(<4 x double>) + +; ACCELERATE: declare <4 x float> @vlog10f(<4 x float>) + +; SLEEFGNUABI: declare <2 x double> @_ZGVnN2v_sin(<2 x double>) +; SLEEFGNUABI: declare <vscale x 2 x double> @_ZGVsMxv_sin(<vscale x 2 x double>, <vscale x 2 x i1>) +; SLEEFGNUABI: declare <4 x float> @_ZGVnN4v_log10f(<4 x float>) +; SLEEFGNUABI: declare <vscale x 4 x float> @_ZGVsMxv_log10f(<vscale x 4 x float>, <vscale x 4 x i1>) + +; ARMPL: declare <2 x double> @armpl_vsinq_f64(<2 x double>) +; ARMPL: declare <vscale x 2 x double> @armpl_svsin_f64_x(<vscale x 2 x double>, <vscale x 2 x i1>) +; ARMPL: declare <4 x float> @armpl_vlog10q_f32(<4 x float>) +; ARMPL: declare <vscale x 4 x float> @armpl_svlog10_f32_x(<vscale x 4 x float>, <vscale x 4 x i1>) + attributes #0 = { nounwind readnone } ; SVML: attributes #[[SIN]] = { "vector-function-abi-variant"= |