diff options
Diffstat (limited to 'llvm/test/MC/RISCV')
| -rw-r--r-- | llvm/test/MC/RISCV/cfi-advance.s | 7 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/fixups-expr.s | 28 |
2 files changed, 35 insertions, 0 deletions
diff --git a/llvm/test/MC/RISCV/cfi-advance.s b/llvm/test/MC/RISCV/cfi-advance.s index d9224fd..c4af390 100644 --- a/llvm/test/MC/RISCV/cfi-advance.s +++ b/llvm/test/MC/RISCV/cfi-advance.s @@ -5,6 +5,8 @@ # CHECK: .rela.eh_frame { # CHECK-NEXT: 0x1C R_RISCV_32_PCREL <null> 0x0 +# CHECK-NEXT: 0x35 R_RISCV_SET6 <null> 0x0 +# CHECK-NEXT: 0x35 R_RISCV_SUB6 <null> 0x0 # CHECK-NEXT: } # CHECK-DWARFDUMP: DW_CFA_advance_loc1: 104 # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 @@ -12,6 +14,8 @@ # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 # CHECK-DWARFDUMP-NEXT: DW_CFA_advance_loc4: 65539 # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 +# CHECK-DWARFDUMP-NEXT: DW_CFA_advance_loc: 10 +# CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 .text .globl test # -- Begin function test .p2align 1 @@ -28,4 +32,7 @@ test: .zero 65535, 0x90 .cfi_def_cfa_offset 8 nop + .p2align 3 + .cfi_def_cfa_offset 8 + nop .cfi_endproc diff --git a/llvm/test/MC/RISCV/fixups-expr.s b/llvm/test/MC/RISCV/fixups-expr.s index 8a02d29..63e7f2e 100644 --- a/llvm/test/MC/RISCV/fixups-expr.s +++ b/llvm/test/MC/RISCV/fixups-expr.s @@ -16,11 +16,15 @@ .globl G1 .globl G2 +.globl G3 .L1: G1: call extern .L2: G2: + .p2align 3 +.L3: +G3: .data .dword .L2-.L1 @@ -31,6 +35,14 @@ G2: .half G2-G1 .byte .L2-.L1 .byte G2-G1 +.dword .L3-.L2 +.dword G3-G2 +.word .L3-.L2 +.word G3-G2 +.half .L3-.L2 +.half G3-G2 +.byte .L3-.L2 +.byte G3-G2 # RELAX: .rela.data { # RELAX-NEXT: 0x0 R_RISCV_ADD64 .L2 0x0 # RELAX-NEXT: 0x0 R_RISCV_SUB64 .L1 0x0 @@ -48,4 +60,20 @@ G2: # RELAX-NEXT: 0x1C R_RISCV_SUB8 .L1 0x0 # RELAX-NEXT: 0x1D R_RISCV_ADD8 G2 0x0 # RELAX-NEXT: 0x1D R_RISCV_SUB8 G1 0x0 +# RELAX-NEXT: 0x1E R_RISCV_ADD64 .L3 0x0 +# RELAX-NEXT: 0x1E R_RISCV_SUB64 .L2 0x0 +# RELAX-NEXT: 0x26 R_RISCV_ADD64 G3 0x0 +# RELAX-NEXT: 0x26 R_RISCV_SUB64 G2 0x0 +# RELAX-NEXT: 0x2E R_RISCV_ADD32 .L3 0x0 +# RELAX-NEXT: 0x2E R_RISCV_SUB32 .L2 0x0 +# RELAX-NEXT: 0x32 R_RISCV_ADD32 G3 0x0 +# RELAX-NEXT: 0x32 R_RISCV_SUB32 G2 0x0 +# RELAX-NEXT: 0x36 R_RISCV_ADD16 .L3 0x0 +# RELAX-NEXT: 0x36 R_RISCV_SUB16 .L2 0x0 +# RELAX-NEXT: 0x38 R_RISCV_ADD16 G3 0x0 +# RELAX-NEXT: 0x38 R_RISCV_SUB16 G2 0x0 +# RELAX-NEXT: 0x3A R_RISCV_ADD8 .L3 0x0 +# RELAX-NEXT: 0x3A R_RISCV_SUB8 .L2 0x0 +# RELAX-NEXT: 0x3B R_RISCV_ADD8 G3 0x0 +# RELAX-NEXT: 0x3B R_RISCV_SUB8 G2 0x0 # RELAX-NEXT: } |