diff options
Diffstat (limited to 'llvm/test/MC/AArch64/SME2')
22 files changed, 3594 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/SME2/bfadd-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfadd-diagnostics.s new file mode 100644 index 0000000..cadb470 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfadd-diagnostics.s @@ -0,0 +1,53 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Out of range index offset + +bfadd za.h[w8, 8], {z20.h-z21.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfadd za.h[w8, 8], {z20.h-z21.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfadd za.h[w8, -1, vgx4], {z0.h-z3.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfadd za.h[w8, -1, vgx4], {z0.h-z3.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector select register + +bfadd za.h[w7, 0], {z20.h-z21.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfadd za.h[w7, 0], {z20.h-z21.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfadd za.h[w12, 0, vgx4], {z20.h-z23.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfadd za.h[w12, 0, vgx4], {z20.h-z23.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfadd za.h[w8, 3], {z20.h-z22.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfadd za.h[w8, 3], {z20.h-z22.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfadd za.h[w8, 3, vgx4], {z21.h-z24.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfadd za.h[w8, 3, vgx4], {z21.h-z24.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid suffixes + +bfadd za.h[w8, 3, vgx4], {z20.s-z23.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfadd za.h[w8, 3, vgx4], {z20.s-z23.s} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfadd za.d[w8, 3, vgx4], {z20.h-z23.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h +// CHECK-NEXT: bfadd za.d[w8, 3, vgx4], {z20.h-z23.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfadd.s b/llvm/test/MC/AArch64/SME2/bfadd.s new file mode 100644 index 0000000..0ba009a --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfadd.s @@ -0,0 +1,300 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfadd za.h[w8, 0, vgx2], {z0.h, z1.h} // 11000001-11100100-00011100-00000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x00,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c00 <unknown> + +bfadd za.h[w8, 0], {z0.h - z1.h} // 11000001-11100100-00011100-00000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x00,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c00 <unknown> + +bfadd za.h[w10, 5, vgx2], {z10.h, z11.h} // 11000001-11100100-01011101-01000101 +// CHECK-INST: bfadd za.h[w10, 5, vgx2], { z10.h, z11.h } +// CHECK-ENCODING: [0x45,0x5d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45d45 <unknown> + +bfadd za.h[w10, 5], {z10.h - z11.h} // 11000001-11100100-01011101-01000101 +// CHECK-INST: bfadd za.h[w10, 5, vgx2], { z10.h, z11.h } +// CHECK-ENCODING: [0x45,0x5d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45d45 <unknown> + +bfadd za.h[w11, 7, vgx2], {z12.h, z13.h} // 11000001-11100100-01111101-10000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x87,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d87 <unknown> + +bfadd za.h[w11, 7], {z12.h - z13.h} // 11000001-11100100-01111101-10000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x87,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d87 <unknown> + +bfadd za.h[w11, 7, vgx2], {z30.h, z31.h} // 11000001-11100100-01111111-11000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx2], { z30.h, z31.h } +// CHECK-ENCODING: [0xc7,0x7f,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47fc7 <unknown> + +bfadd za.h[w11, 7], {z30.h - z31.h} // 11000001-11100100-01111111-11000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx2], { z30.h, z31.h } +// CHECK-ENCODING: [0xc7,0x7f,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47fc7 <unknown> + +bfadd za.h[w8, 5, vgx2], {z16.h, z17.h} // 11000001-11100100-00011110-00000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx2], { z16.h, z17.h } +// CHECK-ENCODING: [0x05,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41e05 <unknown> + +bfadd za.h[w8, 5], {z16.h - z17.h} // 11000001-11100100-00011110-00000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx2], { z16.h, z17.h } +// CHECK-ENCODING: [0x05,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41e05 <unknown> + +bfadd za.h[w8, 1, vgx2], {z0.h, z1.h} // 11000001-11100100-00011100-00000001 +// CHECK-INST: bfadd za.h[w8, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x01,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c01 <unknown> + +bfadd za.h[w8, 1], {z0.h - z1.h} // 11000001-11100100-00011100-00000001 +// CHECK-INST: bfadd za.h[w8, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x01,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c01 <unknown> + +bfadd za.h[w10, 0, vgx2], {z18.h, z19.h} // 11000001-11100100-01011110, 01000000 +// CHECK-INST: bfadd za.h[w10, 0, vgx2], { z18.h, z19.h } +// CHECK-ENCODING: [0x40,0x5e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45e40 <unknown> + +bfadd za.h[w10, 0], {z18.h - z19.h} // 11000001-11100100-01011110-01000000 +// CHECK-INST: bfadd za.h[w10, 0, vgx2], { z18.h, z19.h } +// CHECK-ENCODING: [0x40,0x5e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45e40 <unknown> + +bfadd za.h[w8, 0, vgx2], {z12.h, z13.h} // 11000001-11100100-00011101-10000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x80,0x1d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41d80 <unknown> + +bfadd za.h[w8, 0], {z12.h - z13.h} // 11000001-11100100-00011101-10000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x80,0x1d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41d80 <unknown> + +bfadd za.h[w10, 1, vgx2], {z0.h, z1.h} // 11000001-11100100-01011100-00000001 +// CHECK-INST: bfadd za.h[w10, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x01,0x5c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45c01 <unknown> + +bfadd za.h[w10, 1], {z0.h - z1.h} // 11000001-11100100-01011100-00000001 +// CHECK-INST: bfadd za.h[w10, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x01,0x5c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45c01 <unknown> + +bfadd za.h[w8, 5, vgx2], {z22.h, z23.h} // 11000001-11100100-00011110, 11000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx2], { z22.h, z23.h } +// CHECK-ENCODING: [0xc5,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41ec5 <unknown> + +bfadd za.h[w8, 5], {z22.h - z23.h} // 11000001-11100100-00011110-11000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx2], { z22.h, z23.h } +// CHECK-ENCODING: [0xc5,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41ec5 <unknown> + +bfadd za.h[w11, 2, vgx2], {z8.h, z9.h} // 11000001-11100100-01111101-00000010 +// CHECK-INST: bfadd za.h[w11, 2, vgx2], { z8.h, z9.h } +// CHECK-ENCODING: [0x02,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d02 <unknown> + +bfadd za.h[w11, 2], {z8.h - z9.h} // 11000001-11100100-01111101-00000010 +// CHECK-INST: bfadd za.h[w11, 2, vgx2], { z8.h, z9.h } +// CHECK-ENCODING: [0x02,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d02 <unknown> + +bfadd za.h[w9, 7, vgx2], {z12.h, z13.h} // 11000001-11100100-00111101-10000111 +// CHECK-INST: bfadd za.h[w9, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x87,0x3d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e43d87 <unknown> + +bfadd za.h[w9, 7], {z12.h - z13.h} // 11000001-11100100-00111101-10000111 +// CHECK-INST: bfadd za.h[w9, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x87,0x3d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e43d87 <unknown> + +bfadd za.h[w8, 0, vgx4], {z0.h - z3.h} // 11000001-11100101-00011100-00000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x00,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c00 <unknown> + +bfadd za.h[w8, 0], {z0.h - z3.h} // 11000001-11100101-00011100-00000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x00,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c00 <unknown> + +bfadd za.h[w10, 5, vgx4], {z8.h - z11.h} // 11000001-11100101-01011101-00000101 +// CHECK-INST: bfadd za.h[w10, 5, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x05,0x5d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55d05 <unknown> + +bfadd za.h[w10, 5], {z8.h - z11.h} // 11000001-11100101-01011101-00000101 +// CHECK-INST: bfadd za.h[w10, 5, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x05,0x5d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55d05 <unknown> + +bfadd za.h[w11, 7, vgx4], {z12.h - z15.h} // 11000001-11100101-01111101-10000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x87,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d87 <unknown> + +bfadd za.h[w11, 7], {z12.h - z15.h} // 11000001-11100101-01111101-10000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x87,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d87 <unknown> + +bfadd za.h[w11, 7, vgx4], {z28.h - z31.h} // 11000001-11100101-01111111-10000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx4], { z28.h - z31.h } +// CHECK-ENCODING: [0x87,0x7f,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57f87 <unknown> + +bfadd za.h[w11, 7], {z28.h - z31.h} // 11000001-11100101-01111111-10000111 +// CHECK-INST: bfadd za.h[w11, 7, vgx4], { z28.h - z31.h } +// CHECK-ENCODING: [0x87,0x7f,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57f87 <unknown> + +bfadd za.h[w8, 5, vgx4], {z16.h - z19.h} // 11000001-11100101-00011110-00000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x05,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e05 <unknown> + +bfadd za.h[w8, 5], {z16.h - z19.h} // 11000001-11100101-00011110-00000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x05,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e05 <unknown> + +bfadd za.h[w8, 1, vgx4], {z0.h - z3.h} // 11000001-11100101-00011100-00000001 +// CHECK-INST: bfadd za.h[w8, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x01,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c01 <unknown> + +bfadd za.h[w8, 1], {z0.h - z3.h} // 11000001-11100101-00011100-00000001 +// CHECK-INST: bfadd za.h[w8, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x01,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c01 <unknown> + +bfadd za.h[w10, 0, vgx4], {z16.h - z19.h} // 11000001-11100101-01011110-00000000 +// CHECK-INST: bfadd za.h[w10, 0, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x00,0x5e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55e00 <unknown> + +bfadd za.h[w10, 0], {z16.h - z19.h} // 11000001-11100101-01011110-00000000 +// CHECK-INST: bfadd za.h[w10, 0, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x00,0x5e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55e00 <unknown> + +bfadd za.h[w8, 0, vgx4], {z12.h - z15.h} // 11000001-11100101-00011101-10000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x80,0x1d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51d80 <unknown> + +bfadd za.h[w8, 0], {z12.h - z15.h} // 11000001-11100101-00011101-10000000 +// CHECK-INST: bfadd za.h[w8, 0, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x80,0x1d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51d80 <unknown> + +bfadd za.h[w10, 1, vgx4], {z0.h - z3.h} // 11000001-11100101-01011100-00000001 +// CHECK-INST: bfadd za.h[w10, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x01,0x5c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55c01 <unknown> + +bfadd za.h[w10, 1], {z0.h - z3.h} // 11000001-11100101-01011100-00000001 +// CHECK-INST: bfadd za.h[w10, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x01,0x5c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55c01 <unknown> + +bfadd za.h[w8, 5, vgx4], {z20.h - z23.h} // 11000001-11100101-00011110-10000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx4], { z20.h - z23.h } +// CHECK-ENCODING: [0x85,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e85 <unknown> + +bfadd za.h[w8, 5], {z20.h - z23.h} // 11000001-11100101-00011110-10000101 +// CHECK-INST: bfadd za.h[w8, 5, vgx4], { z20.h - z23.h } +// CHECK-ENCODING: [0x85,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e85 <unknown> + +bfadd za.h[w11, 2, vgx4], {z8.h - z11.h} // 11000001-11100101-01111101-00000010 +// CHECK-INST: bfadd za.h[w11, 2, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x02,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d02 <unknown> + +bfadd za.h[w11, 2], {z8.h - z11.h} // 11000001-11100101-01111101-00000010 +// CHECK-INST: bfadd za.h[w11, 2, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x02,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d02 <unknown> + +bfadd za.h[w9, 7, vgx4], {z12.h - z15.h} // 11000001-11100101-00111101-10000111 +// CHECK-INST: bfadd za.h[w9, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x87,0x3d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e53d87 <unknown> + +bfadd za.h[w9, 7], {z12.h - z15.h} // 11000001-11100101-00111101-10000111 +// CHECK-INST: bfadd za.h[w9, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x87,0x3d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e53d87 <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfclamp-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfclamp-diagnostics.s new file mode 100644 index 0000000..661cfad --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfclamp-diagnostics.s @@ -0,0 +1,33 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfclamp {z0.h-z2.h}, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfclamp {z0.h-z2.h}, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfclamp {z23.h-z24.h}, z13.h, z8.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfclamp {z23.h-z24.h}, z13.h, z8.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfclamp {z21.h-z24.h}, z10.h, z21.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfclamp {z21.h-z24.h}, z10.h, z21.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfclamp {z0.s-z1.s}, z0.h, z4.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfclamp {z0.s-z1.s}, z0.h, z4.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfclamp {z0.h-z3.h}, z5.d, z6.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfclamp {z0.h-z3.h}, z5.d, z6.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfclamp.s b/llvm/test/MC/AArch64/SME2/bfclamp.s new file mode 100644 index 0000000..dc3caec --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfclamp.s @@ -0,0 +1,60 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfclamp {z0.h, z1.h}, z0.h, z0.h // 11000001-00100000-11000000-00000000 +// CHECK-INST: bfclamp { z0.h, z1.h }, z0.h, z0.h +// CHECK-ENCODING: [0x00,0xc0,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120c000 <unknown> + +bfclamp {z20.h, z21.h}, z10.h, z21.h // 11000001-00110101-11000001-01010100 +// CHECK-INST: bfclamp { z20.h, z21.h }, z10.h, z21.h +// CHECK-ENCODING: [0x54,0xc1,0x35,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c135c154 <unknown> + +bfclamp {z22.h, z23.h}, z13.h, z8.h // 11000001-00101000-11000001-10110110 +// CHECK-INST: bfclamp { z22.h, z23.h }, z13.h, z8.h +// CHECK-ENCODING: [0xb6,0xc1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128c1b6 <unknown> + +bfclamp {z30.h, z31.h}, z31.h, z31.h // 11000001-00111111-11000011-11111110 +// CHECK-INST: bfclamp { z30.h, z31.h }, z31.h, z31.h +// CHECK-ENCODING: [0xfe,0xc3,0x3f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13fc3fe <unknown> + +bfclamp {z0.h - z3.h}, z0.h, z0.h // 11000001-00100000-11001000-00000000 +// CHECK-INST: bfclamp { z0.h - z3.h }, z0.h, z0.h +// CHECK-ENCODING: [0x00,0xc8,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120c800 <unknown> + +bfclamp {z20.h - z23.h}, z10.h, z21.h // 11000001-00110101-11001001-01010100 +// CHECK-INST: bfclamp { z20.h - z23.h }, z10.h, z21.h +// CHECK-ENCODING: [0x54,0xc9,0x35,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c135c954 <unknown> + +bfclamp {z20.h - z23.h}, z13.h, z8.h // 11000001-00101000-11001001-10110100 +// CHECK-INST: bfclamp { z20.h - z23.h }, z13.h, z8.h +// CHECK-ENCODING: [0xb4,0xc9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128c9b4 <unknown> + +bfclamp {z28.h - z31.h}, z31.h, z31.h // 11000001-00111111-11001011-11111100 +// CHECK-INST: bfclamp { z28.h - z31.h }, z31.h, z31.h +// CHECK-ENCODING: [0xfc,0xcb,0x3f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13fcbfc <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfmax-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmax-diagnostics.s new file mode 100644 index 0000000..bbb619e --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmax-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfmax {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmax {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmax {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfmax {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmax {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfmax {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid single register + +bfmax {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmax {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfmax {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmax {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmax {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmax {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmax {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: bfmax {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmax.s b/llvm/test/MC/AArch64/SME2/bfmax.s new file mode 100644 index 0000000..657fcbc --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmax.s @@ -0,0 +1,108 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmax {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-00100000-10100001-00000000 +// CHECK-INST: bfmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x00,0xa1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a100 <unknown> + +bfmax {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-00100101-10100001-00010100 +// CHECK-INST: bfmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h +// CHECK-ENCODING: [0x14,0xa1,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a114 <unknown> + +bfmax {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-00101000-10100001-00010110 +// CHECK-INST: bfmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h +// CHECK-ENCODING: [0x16,0xa1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a116 <unknown> + +bfmax {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-00101111-10100001-00011110 +// CHECK-INST: bfmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h +// CHECK-ENCODING: [0x1e,0xa1,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa11e <unknown> + +bfmax {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-00100000-10110001-00000000 +// CHECK-INST: bfmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x00,0xb1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b100 <unknown> + +bfmax {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-00110100-10110001-00010100 +// CHECK-INST: bfmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x14,0xb1,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b114 <unknown> + +bfmax {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-00101000-10110001-00010110 +// CHECK-INST: bfmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x16,0xb1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b116 <unknown> + +bfmax {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-00111110-10110001-00011110 +// CHECK-INST: bfmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x1e,0xb1,0x3e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13eb11e <unknown> + +bfmax {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-00100000-10101001-00000000 +// CHECK-INST: bfmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x00,0xa9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a900 <unknown> + +bfmax {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-00100101-10101001-00010100 +// CHECK-INST: bfmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h +// CHECK-ENCODING: [0x14,0xa9,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a914 <unknown> + +bfmax {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-00101000-10101001-00010100 +// CHECK-INST: bfmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h +// CHECK-ENCODING: [0x14,0xa9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a914 <unknown> + +bfmax {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-00101111-10101001-00011100 +// CHECK-INST: bfmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h +// CHECK-ENCODING: [0x1c,0xa9,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa91c <unknown> + +bfmax {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-00100000-10111001-00000000 +// CHECK-INST: bfmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x00,0xb9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b900 <unknown> + +bfmax {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-00110100-10111001-00010100 +// CHECK-INST: bfmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x14,0xb9,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b914 <unknown> + +bfmax {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-00101000-10111001-00010100 +// CHECK-INST: bfmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x14,0xb9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b914 <unknown> + +bfmax {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-00111100-10111001-00011100 +// CHECK-INST: bfmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x1c,0xb9,0x3c,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13cb91c <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfmaxnm-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmaxnm-diagnostics.s new file mode 100644 index 0000000..ab837b6 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmaxnm-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfmaxnm {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmaxnm {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmaxnm {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfmaxnm {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmaxnm {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfmaxnm {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid single register + +bfmaxnm {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmaxnm {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfmaxnm {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmaxnm {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmaxnm {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmaxnm {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmaxnm {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: bfmaxnm {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmaxnm.s b/llvm/test/MC/AArch64/SME2/bfmaxnm.s new file mode 100644 index 0000000..f61f530 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmaxnm.s @@ -0,0 +1,108 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmaxnm {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-00100000-10100001-00100000 +// CHECK-INST: bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x20,0xa1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a120 <unknown> + +bfmaxnm {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-00100101-10100001-00110100 +// CHECK-INST: bfmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h +// CHECK-ENCODING: [0x34,0xa1,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a134 <unknown> + +bfmaxnm {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-00101000-10100001-00110110 +// CHECK-INST: bfmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h +// CHECK-ENCODING: [0x36,0xa1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a136 <unknown> + +bfmaxnm {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-00101111-10100001-00111110 +// CHECK-INST: bfmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h +// CHECK-ENCODING: [0x3e,0xa1,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa13e <unknown> + +bfmaxnm {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-00100000-10110001-00100000 +// CHECK-INST: bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x20,0xb1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b120 <unknown> + +bfmaxnm {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-00110100-10110001-00110100 +// CHECK-INST: bfmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x34,0xb1,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b134 <unknown> + +bfmaxnm {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-00101000-10110001-00110110 +// CHECK-INST: bfmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x36,0xb1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b136 <unknown> + +bfmaxnm {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-00111110-10110001-00111110 +// CHECK-INST: bfmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x3e,0xb1,0x3e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13eb13e <unknown> + +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-00100000-10101001-00100000 +// CHECK-INST: bfmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x20,0xa9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a920 <unknown> + +bfmaxnm {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-00100101-10101001-00110100 +// CHECK-INST: bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h +// CHECK-ENCODING: [0x34,0xa9,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a934 <unknown> + +bfmaxnm {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-00101000-10101001-00110100 +// CHECK-INST: bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h +// CHECK-ENCODING: [0x34,0xa9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a934 <unknown> + +bfmaxnm {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-00101111-10101001-00111100 +// CHECK-INST: bfmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h +// CHECK-ENCODING: [0x3c,0xa9,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa93c <unknown> + +bfmaxnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-00100000-10111001-00100000 +// CHECK-INST: bfmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x20,0xb9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b920 <unknown> + +bfmaxnm {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-00110100-10111001-00110100 +// CHECK-INST: bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x34,0xb9,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b934 <unknown> + +bfmaxnm {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-00101000-10111001-00110100 +// CHECK-INST: bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x34,0xb9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b934 <unknown> + +bfmaxnm {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-00111100-10111001-00111100 +// CHECK-INST: bfmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x3c,0xb9,0x3c,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13cb93c <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfmin-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmin-diagnostics.s new file mode 100644 index 0000000..41f1036 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmin-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfmin {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmin {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmin {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfmin {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmin {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfmin {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid single register + +bfmin {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfmin {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmin {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmin {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmin.s b/llvm/test/MC/AArch64/SME2/bfmin.s new file mode 100644 index 0000000..6612e3c --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmin.s @@ -0,0 +1,108 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmin {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-00100000-10100001-00000001 +// CHECK-INST: bfmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x01,0xa1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a101 <unknown> + +bfmin {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-00100101-10100001-00010101 +// CHECK-INST: bfmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h +// CHECK-ENCODING: [0x15,0xa1,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a115 <unknown> + +bfmin {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-00101000-10100001-00010111 +// CHECK-INST: bfmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h +// CHECK-ENCODING: [0x17,0xa1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a117 <unknown> + +bfmin {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-00101111-10100001-00011111 +// CHECK-INST: bfmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h +// CHECK-ENCODING: [0x1f,0xa1,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa11f <unknown> + +bfmin {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-00100000-10110001-00000001 +// CHECK-INST: bfmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x01,0xb1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b101 <unknown> + +bfmin {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-00110100-10110001-00010101 +// CHECK-INST: bfmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x15,0xb1,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b115 <unknown> + +bfmin {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-00101000-10110001-00010111 +// CHECK-INST: bfmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x17,0xb1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b117 <unknown> + +bfmin {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-00111110-10110001-00011111 +// CHECK-INST: bfmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x1f,0xb1,0x3e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13eb11f <unknown> + +bfmin {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-00100000-10101001-00000001 +// CHECK-INST: bfmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x01,0xa9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a901 <unknown> + +bfmin {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-00100101-10101001-00010101 +// CHECK-INST: bfmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h +// CHECK-ENCODING: [0x15,0xa9,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a915 <unknown> + +bfmin {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-00101000-10101001-00010101 +// CHECK-INST: bfmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h +// CHECK-ENCODING: [0x15,0xa9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a915 <unknown> + +bfmin {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-00101111-10101001-00011101 +// CHECK-INST: bfmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h +// CHECK-ENCODING: [0x1d,0xa9,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa91d <unknown> + +bfmin {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-00100000-10111001-00000001 +// CHECK-INST: bfmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x01,0xb9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b901 <unknown> + +bfmin {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-00110100-10111001-00010101 +// CHECK-INST: bfmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x15,0xb9,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b915 <unknown> + +bfmin {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-00101000-10111001-00010101 +// CHECK-INST: bfmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x15,0xb9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b915 <unknown> + +bfmin {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-00111100-10111001-00011101 +// CHECK-INST: bfmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x1d,0xb9,0x3c,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13cb91d <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfminnm-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfminnm-diagnostics.s new file mode 100644 index 0000000..14485e9 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfminnm-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfminnm {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfminnm {z0.h-z1.h}, {z0.h-z2.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfminnm {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfminnm {z1.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfminnm {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfminnm {z1.h-z4.h}, {z0.h-z3.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid single register + +bfminnm {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfminnm {z0.h-z1.h}, {z2.h-z3.h}, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfminnm {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfminnm {z0.h-z1.h}, {z2.h-z3.h}, z14.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfminnm {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfminnm {z0.h-z1.h}, {z2.s-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfminnm {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: bfminnm {z0.h-z1.h}, {z2.h-z3.s}, z14.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfminnm.s b/llvm/test/MC/AArch64/SME2/bfminnm.s new file mode 100644 index 0000000..4a48a0d --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfminnm.s @@ -0,0 +1,113 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +bfminnm {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-00100000-10100001-00100001 +// CHECK-INST: bfminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x21,0xa1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a121 <unknown> + +bfminnm {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-00100101-10100001-00110101 +// CHECK-INST: bfminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h +// CHECK-ENCODING: [0x35,0xa1,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a135 <unknown> + +bfminnm {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-00101000-10100001-00110111 +// CHECK-INST: bfminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h +// CHECK-ENCODING: [0x37,0xa1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a137 <unknown> + +bfminnm {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-00101111-10100001-00111111 +// CHECK-INST: bfminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h +// CHECK-ENCODING: [0x3f,0xa1,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa13f <unknown> + + +bfminnm {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-00100000-10110001-00100001 +// CHECK-INST: bfminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x21,0xb1,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b121 <unknown> + +bfminnm {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-00110100-10110001-00110101 +// CHECK-INST: bfminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x35,0xb1,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b135 <unknown> + +bfminnm {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-00101000-10110001-00110111 +// CHECK-INST: bfminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x37,0xb1,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b137 <unknown> + +bfminnm {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-00111110-10110001-00111111 +// CHECK-INST: bfminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x3f,0xb1,0x3e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13eb13f <unknown> + + +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-00100000-10101001-00100001 +// CHECK-INST: bfminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x21,0xa9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120a921 <unknown> + +bfminnm {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-00100101-10101001-00110101 +// CHECK-INST: bfminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h +// CHECK-ENCODING: [0x35,0xa9,0x25,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c125a935 <unknown> + +bfminnm {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-00101000-10101001-00110101 +// CHECK-INST: bfminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h +// CHECK-ENCODING: [0x35,0xa9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128a935 <unknown> + +bfminnm {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-00101111-10101001-00111101 +// CHECK-INST: bfminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h +// CHECK-ENCODING: [0x3d,0xa9,0x2f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c12fa93d <unknown> + + +bfminnm {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-00100000-10111001-00100001 +// CHECK-INST: bfminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x21,0xb9,0x20,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c120b921 <unknown> + +bfminnm {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-00110100-10111001-00110101 +// CHECK-INST: bfminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x35,0xb9,0x34,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c134b935 <unknown> + +bfminnm {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-00101000-10111001-00110101 +// CHECK-INST: bfminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x35,0xb9,0x28,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c128b935 <unknown> + +bfminnm {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-00111100-10111001-00111101 +// CHECK-INST: bfminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x3d,0xb9,0x3c,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c13cb93d <unknown> + diff --git a/llvm/test/MC/AArch64/SME2/bfmla-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmla-diagnostics.s new file mode 100644 index 0000000..efd2624 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmla-diagnostics.s @@ -0,0 +1,94 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfmla za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmla za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: bfmla za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfmla za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfmla za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid indexed-vector or single-vector register + +bfmla za.h[w8, 0], {z0.h-z1.h}, z16.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmla za.h[w8, 0], {z0.h-z1.h}, z16.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w8, 1], {z0.h-z3.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmla za.h[w8, 1], {z0.h-z3.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector select register + +bfmla za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfmla za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfmla za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector select offset + +bfmla za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfmla za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h +// CHECK-NEXT: bfmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector lane index + +bfmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmla.s b/llvm/test/MC/AArch64/SME2/bfmla.s new file mode 100644 index 0000000..75ccccc --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmla.s @@ -0,0 +1,876 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmla za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h // 11000001-01100000-00011100-00000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x00,0x1c,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601c00 <unknown> + +bfmla za.h[w8, 0], {z0.h - z1.h}, z0.h // 11000001-01100000-00011100-00000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x00,0x1c,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601c00 <unknown> + +bfmla za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h // 11000001-01100101-01011101-01000101 +// CHECK-INST: bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h +// CHECK-ENCODING: [0x45,0x5d,0x65,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1655d45 <unknown> + +bfmla za.h[w10, 5], {z10.h - z11.h}, z5.h // 11000001-01100101-01011101-01000101 +// CHECK-INST: bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h +// CHECK-ENCODING: [0x45,0x5d,0x65,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1655d45 <unknown> + +bfmla za.h[w11, 7, vgx2], {z13.h, z14.h}, z8.h // 11000001-01101000-01111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h +// CHECK-ENCODING: [0xa7,0x7d,0x68,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1687da7 <unknown> + +bfmla za.h[w11, 7], {z13.h - z14.h}, z8.h // 11000001-01101000-01111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h +// CHECK-ENCODING: [0xa7,0x7d,0x68,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1687da7 <unknown> + +bfmla za.h[w11, 7, vgx2], {z31.h, z0.h}, z15.h // 11000001-01101111-01111111-11100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h +// CHECK-ENCODING: [0xe7,0x7f,0x6f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16f7fe7 <unknown> + +bfmla za.h[w11, 7], {z31.h - z0.h}, z15.h // 11000001-01101111-01111111-11100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h +// CHECK-ENCODING: [0xe7,0x7f,0x6f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16f7fe7 <unknown> + +bfmla za.h[w8, 5, vgx2], {z17.h, z18.h}, z0.h // 11000001-01100000-00011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h +// CHECK-ENCODING: [0x25,0x1e,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601e25 <unknown> + +bfmla za.h[w8, 5], {z17.h - z18.h}, z0.h // 11000001-01100000-00011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h +// CHECK-ENCODING: [0x25,0x1e,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601e25 <unknown> + +bfmla za.h[w8, 1, vgx2], {z1.h, z2.h}, z14.h // 11000001-01101110-00011100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h +// CHECK-ENCODING: [0x21,0x1c,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1c21 <unknown> + +bfmla za.h[w8, 1], {z1.h - z2.h}, z14.h // 11000001-01101110-00011100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h +// CHECK-ENCODING: [0x21,0x1c,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1c21 <unknown> + +bfmla za.h[w10, 0, vgx2], {z19.h, z20.h}, z4.h // 11000001-01100100-01011110-01100000 +// CHECK-INST: bfmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h +// CHECK-ENCODING: [0x60,0x5e,0x64,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1645e60 <unknown> + +bfmla za.h[w10, 0], {z19.h - z20.h}, z4.h // 11000001-01100100-01011110-01100000 +// CHECK-INST: bfmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h +// CHECK-ENCODING: [0x60,0x5e,0x64,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1645e60 <unknown> + +bfmla za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h // 11000001-01100010-00011101-10000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h +// CHECK-ENCODING: [0x80,0x1d,0x62,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1621d80 <unknown> + +bfmla za.h[w8, 0], {z12.h - z13.h}, z2.h // 11000001-01100010-00011101-10000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h +// CHECK-ENCODING: [0x80,0x1d,0x62,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1621d80 <unknown> + +bfmla za.h[w10, 1, vgx2], {z1.h, z2.h}, z10.h // 11000001-01101010-01011100-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h +// CHECK-ENCODING: [0x21,0x5c,0x6a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16a5c21 <unknown> + +bfmla za.h[w10, 1], {z1.h - z2.h}, z10.h // 11000001-01101010-01011100-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h +// CHECK-ENCODING: [0x21,0x5c,0x6a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16a5c21 <unknown> + +bfmla za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h // 11000001-01101110-00011110-11000101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h +// CHECK-ENCODING: [0xc5,0x1e,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1ec5 <unknown> + +bfmla za.h[w8, 5], {z22.h - z23.h}, z14.h // 11000001-01101110-00011110-11000101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h +// CHECK-ENCODING: [0xc5,0x1e,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1ec5 <unknown> + +bfmla za.h[w11, 2, vgx2], {z9.h, z10.h}, z1.h // 11000001-01100001-01111101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h +// CHECK-ENCODING: [0x22,0x7d,0x61,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1617d22 <unknown> + +bfmla za.h[w11, 2], {z9.h - z10.h}, z1.h // 11000001-01100001-01111101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h +// CHECK-ENCODING: [0x22,0x7d,0x61,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1617d22 <unknown> + +bfmla za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h // 11000001-01101011-00111101-10000111 +// CHECK-INST: bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h +// CHECK-ENCODING: [0x87,0x3d,0x6b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16b3d87 <unknown> + +bfmla za.h[w9, 7], {z12.h - z13.h}, z11.h // 11000001-01101011-00111101-10000111 +// CHECK-INST: bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h +// CHECK-ENCODING: [0x87,0x3d,0x6b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16b3d87 <unknown> + +bfmla za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-00010000-00010000-00100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] +// CHECK-ENCODING: [0x20,0x10,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101020 <unknown> + +bfmla za.h[w8, 0], {z0.h - z1.h}, z0.h[0] // 11000001-00010000-00010000-00100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] +// CHECK-ENCODING: [0x20,0x10,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101020 <unknown> + +bfmla za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h[2] // 11000001-00010101-01010101-01100101 +// CHECK-INST: bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] +// CHECK-ENCODING: [0x65,0x55,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1155565 <unknown> + +bfmla za.h[w10, 5], {z10.h - z11.h}, z5.h[2] // 11000001-00010101-01010101-01100101 +// CHECK-INST: bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] +// CHECK-ENCODING: [0x65,0x55,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1155565 <unknown> + +bfmla za.h[w11, 7, vgx2], {z12.h, z13.h}, z8.h[6] // 11000001-00011000-01111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] +// CHECK-ENCODING: [0xa7,0x7d,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1187da7 <unknown> + +bfmla za.h[w11, 7], {z12.h - z13.h}, z8.h[6] // 11000001-00011000-01111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] +// CHECK-ENCODING: [0xa7,0x7d,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1187da7 <unknown> + +bfmla za.h[w11, 7, vgx2], {z30.h, z31.h}, z15.h[7] // 11000001-00011111-01111111-11101111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] +// CHECK-ENCODING: [0xef,0x7f,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11f7fef <unknown> + +bfmla za.h[w11, 7], {z30.h - z31.h}, z15.h[7] // 11000001-00011111-01111111-11101111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] +// CHECK-ENCODING: [0xef,0x7f,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11f7fef <unknown> + +bfmla za.h[w8, 5, vgx2], {z16.h, z17.h}, z0.h[6] // 11000001-00010000-00011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] +// CHECK-ENCODING: [0x25,0x1e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101e25 <unknown> + +bfmla za.h[w8, 5], {z16.h - z17.h}, z0.h[6] // 11000001-00010000-00011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] +// CHECK-ENCODING: [0x25,0x1e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101e25 <unknown> + +bfmla za.h[w8, 1, vgx2], {z0.h, z1.h}, z14.h[2] // 11000001-00011110-00010100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] +// CHECK-ENCODING: [0x21,0x14,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1421 <unknown> + +bfmla za.h[w8, 1], {z0.h - z1.h}, z14.h[2] // 11000001-00011110-00010100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] +// CHECK-ENCODING: [0x21,0x14,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1421 <unknown> + +bfmla za.h[w10, 0, vgx2], {z18.h, z19.h}, z4.h[3] // 11000001-00010100-01010110-01101000 +// CHECK-INST: bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] +// CHECK-ENCODING: [0x68,0x56,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1145668 <unknown> + +bfmla za.h[w10, 0], {z18.h - z19.h}, z4.h[3] // 11000001-00010100-01010110-01101000 +// CHECK-INST: bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] +// CHECK-ENCODING: [0x68,0x56,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1145668 <unknown> + +bfmla za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h[4] // 11000001-00010010-00011001-10100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] +// CHECK-ENCODING: [0xa0,0x19,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11219a0 <unknown> + +bfmla za.h[w8, 0], {z12.h - z13.h}, z2.h[4] // 11000001-00010010-00011001-10100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] +// CHECK-ENCODING: [0xa0,0x19,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11219a0 <unknown> + +bfmla za.h[w10, 1, vgx2], {z0.h, z1.h}, z10.h[4] // 11000001-00011010-01011000-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] +// CHECK-ENCODING: [0x21,0x58,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11a5821 <unknown> + +bfmla za.h[w10, 1], {z0.h - z1.h}, z10.h[4] // 11000001-00011010-01011000-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] +// CHECK-ENCODING: [0x21,0x58,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11a5821 <unknown> + +bfmla za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h[5] // 11000001-00011110-00011010-11101101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] +// CHECK-ENCODING: [0xed,0x1a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1aed <unknown> + +bfmla za.h[w8, 5], {z22.h - z23.h}, z14.h[5] // 11000001-00011110-00011010-11101101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] +// CHECK-ENCODING: [0xed,0x1a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1aed <unknown> + +bfmla za.h[w11, 2, vgx2], {z8.h, z9.h}, z1.h[2] // 11000001-00010001-01110101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] +// CHECK-ENCODING: [0x22,0x75,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1117522 <unknown> + +bfmla za.h[w11, 2], {z8.h - z9.h}, z1.h[2] // 11000001-00010001-01110101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] +// CHECK-ENCODING: [0x22,0x75,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1117522 <unknown> + +bfmla za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h[4] // 11000001-00011011-00111001-10100111 +// CHECK-INST: bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] +// CHECK-ENCODING: [0xa7,0x39,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11b39a7 <unknown> + +bfmla za.h[w9, 7], {z12.h - z13.h}, z11.h[4] // 11000001-00011011-00111001-10100111 +// CHECK-INST: bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] +// CHECK-ENCODING: [0xa7,0x39,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11b39a7 <unknown> + +bfmla za.h[w8, 0, vgx2], {z0.h, z1.h}, {z0.h, z1.h} // 11000001, 11100000-00010000-00001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x08,0x10,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e01008 <unknown> + +bfmla za.h[w8, 0], {z0.h - z1.h}, {z0.h - z1.h} // 11000001-11100000-00010000-00001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x08,0x10,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e01008 <unknown> + +bfmla za.h[w10, 5, vgx2], {z10.h, z11.h}, {z20.h, z21.h} // 11000001, 11110100-01010001-01001101 +// CHECK-INST: bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x51,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f4514d <unknown> + +bfmla za.h[w10, 5], {z10.h - z11.h}, {z20.h - z21.h} // 11000001-11110100-01010001-01001101 +// CHECK-INST: bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x4d,0x51,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f4514d <unknown> + +bfmla za.h[w11, 7, vgx2], {z12.h, z13.h}, {z8.h, z9.h} // 11000001, 11101000-01110001-10001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x8f,0x71,0xe8,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e8718f <unknown> + +bfmla za.h[w11, 7], {z12.h - z13.h}, {z8.h - z9.h} // 11000001-11101000-01110001-10001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x8f,0x71,0xe8,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e8718f <unknown> + +bfmla za.h[w11, 7, vgx2], {z30.h, z31.h}, {z30.h, z31.h} // 11000001, 11111110-01110011-11001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x73,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe73cf <unknown> + +bfmla za.h[w11, 7], {z30.h - z31.h}, {z30.h - z31.h} // 11000001-11111110-01110011-11001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x73,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe73cf <unknown> + +bfmla za.h[w8, 5, vgx2], {z16.h, z17.h}, {z16.h, z17.h} // 11000001, 11110000-00010010-00001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x0d,0x12,0xf0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f0120d <unknown> + +bfmla za.h[w8, 5], {z16.h - z17.h}, {z16.h - z17.h} // 11000001-11110000-00010010-00001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x0d,0x12,0xf0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f0120d <unknown> + +bfmla za.h[w8, 1, vgx2], {z0.h, z1.h}, {z30.h, z31.h} // 11000001, 11111110-00010000-00001001 +// CHECK-INST: bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x09,0x10,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe1009 <unknown> + +bfmla za.h[w8, 1], {z0.h - z1.h}, {z30.h - z31.h} // 11000001-11111110-00010000-00001001 +// CHECK-INST: bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x09,0x10,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe1009 <unknown> + +bfmla za.h[w10, 0, vgx2], {z18.h, z19.h}, {z20.h, z21.h} // 11000001, 11110100-01010010-01001000 +// CHECK-INST: bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x48,0x52,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f45248 <unknown> + +bfmla za.h[w10, 0], {z18.h - z19.h}, {z20.h - z21.h} // 11000001-11110100-01010010-01001000 +// CHECK-INST: bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x48,0x52,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f45248 <unknown> + +bfmla za.h[w8, 0, vgx2], {z12.h, z13.h}, {z2.h, z3.h} // 11000001, 11100010-00010001-10001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } +// CHECK-ENCODING: [0x88,0x11,0xe2,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e21188 <unknown> + +bfmla za.h[w8, 0], {z12.h - z13.h}, {z2.h - z3.h} // 11000001-11100010-00010001-10001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } +// CHECK-ENCODING: [0x88,0x11,0xe2,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e21188 <unknown> + +bfmla za.h[w10, 1, vgx2], {z0.h, z1.h}, {z26.h, z27.h} // 11000001, 11111010-01010000-00001001 +// CHECK-INST: bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } +// CHECK-ENCODING: [0x09,0x50,0xfa,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fa5009 <unknown> + +bfmla za.h[w10, 1], {z0.h - z1.h}, {z26.h - z27.h} // 11000001-11111010-01010000-00001001 +// CHECK-INST: bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } +// CHECK-ENCODING: [0x09,0x50,0xfa,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fa5009 <unknown> + +bfmla za.h[w8, 5, vgx2], {z22.h, z23.h}, {z30.h, z31.h} // 11000001, 11111110-00010010-11001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcd,0x12,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe12cd <unknown> + +bfmla za.h[w8, 5], {z22.h - z23.h}, {z30.h - z31.h} // 11000001-11111110-00010010-11001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xcd,0x12,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe12cd <unknown> + +bfmla za.h[w11, 2, vgx2], {z8.h, z9.h}, {z0.h, z1.h} // 11000001, 11100000-01110001-00001010 +// CHECK-INST: bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x0a,0x71,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e0710a <unknown> + +bfmla za.h[w11, 2], {z8.h - z9.h}, {z0.h - z1.h} // 11000001-11100000-01110001-00001010 +// CHECK-INST: bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x0a,0x71,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e0710a <unknown> + +bfmla za.h[w9, 7, vgx2], {z12.h, z13.h}, {z10.h, z11.h} // 11000001, 11101010-00110001-10001111 +// CHECK-INST: bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } +// CHECK-ENCODING: [0x8f,0x31,0xea,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1ea318f <unknown> + +bfmla za.h[w9, 7], {z12.h - z13.h}, {z10.h - z11.h} // 11000001-11101010-00110001-10001111 +// CHECK-INST: bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } +// CHECK-ENCODING: [0x8f,0x31,0xea,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1ea318f <unknown> + +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h // 11000001-01110000-00011100-00000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x00,0x1c,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701c00 <unknown> + +bfmla za.h[w8, 0], {z0.h - z3.h}, z0.h // 11000001-01110000-00011100-00000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x00,0x1c,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701c00 <unknown> + +bfmla za.h[w10, 5, vgx4], {z10.h - z13.h}, z5.h // 11000001-01110101-01011101-01000101 +// CHECK-INST: bfmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h +// CHECK-ENCODING: [0x45,0x5d,0x75,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1755d45 <unknown> + +bfmla za.h[w10, 5], {z10.h - z13.h}, z5.h // 11000001-01110101-01011101-01000101 +// CHECK-INST: bfmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h +// CHECK-ENCODING: [0x45,0x5d,0x75,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1755d45 <unknown> + +bfmla za.h[w11, 7, vgx4], {z13.h - z16.h}, z8.h // 11000001-01111000-01111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h +// CHECK-ENCODING: [0xa7,0x7d,0x78,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1787da7 <unknown> + +bfmla za.h[w11, 7], {z13.h - z16.h}, z8.h // 11000001-01111000-01111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h +// CHECK-ENCODING: [0xa7,0x7d,0x78,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1787da7 <unknown> + +bfmla za.h[w11, 7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-01111111-01111111-11100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h +// CHECK-ENCODING: [0xe7,0x7f,0x7f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17f7fe7 <unknown> + +bfmla za.h[w11, 7], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-01111111-01111111-11100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h +// CHECK-ENCODING: [0xe7,0x7f,0x7f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17f7fe7 <unknown> + +bfmla za.h[w8, 5, vgx4], {z17.h - z20.h}, z0.h // 11000001-01110000-00011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h +// CHECK-ENCODING: [0x25,0x1e,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701e25 <unknown> + +bfmla za.h[w8, 5], {z17.h - z20.h}, z0.h // 11000001-01110000-00011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h +// CHECK-ENCODING: [0x25,0x1e,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701e25 <unknown> + +bfmla za.h[w8, 1, vgx4], {z1.h - z4.h}, z14.h // 11000001-01111110-00011100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h +// CHECK-ENCODING: [0x21,0x1c,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1c21 <unknown> + +bfmla za.h[w8, 1], {z1.h - z4.h}, z14.h // 11000001-01111110-00011100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h +// CHECK-ENCODING: [0x21,0x1c,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1c21 <unknown> + +bfmla za.h[w10, 0, vgx4], {z19.h - z22.h}, z4.h // 11000001-01110100-01011110-01100000 +// CHECK-INST: bfmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h +// CHECK-ENCODING: [0x60,0x5e,0x74,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1745e60 <unknown> + +bfmla za.h[w10, 0], {z19.h - z22.h}, z4.h // 11000001-01110100-01011110-01100000 +// CHECK-INST: bfmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h +// CHECK-ENCODING: [0x60,0x5e,0x74,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1745e60 <unknown> + +bfmla za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h // 11000001-01110010-00011101-10000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h +// CHECK-ENCODING: [0x80,0x1d,0x72,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1721d80 <unknown> + +bfmla za.h[w8, 0], {z12.h - z15.h}, z2.h // 11000001-01110010-00011101-10000000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h +// CHECK-ENCODING: [0x80,0x1d,0x72,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1721d80 <unknown> + +bfmla za.h[w10, 1, vgx4], {z1.h - z4.h}, z10.h // 11000001-01111010-01011100-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h +// CHECK-ENCODING: [0x21,0x5c,0x7a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17a5c21 <unknown> + +bfmla za.h[w10, 1], {z1.h - z4.h}, z10.h // 11000001-01111010-01011100-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h +// CHECK-ENCODING: [0x21,0x5c,0x7a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17a5c21 <unknown> + +bfmla za.h[w8, 5, vgx4], {z22.h - z25.h}, z14.h // 11000001-01111110-00011110-11000101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h +// CHECK-ENCODING: [0xc5,0x1e,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1ec5 <unknown> + +bfmla za.h[w8, 5], {z22.h - z25.h}, z14.h // 11000001-01111110-00011110-11000101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h +// CHECK-ENCODING: [0xc5,0x1e,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1ec5 <unknown> + +bfmla za.h[w11, 2, vgx4], {z9.h - z12.h}, z1.h // 11000001-01110001-01111101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h +// CHECK-ENCODING: [0x22,0x7d,0x71,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1717d22 <unknown> + +bfmla za.h[w11, 2], {z9.h - z12.h}, z1.h // 11000001-01110001-01111101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h +// CHECK-ENCODING: [0x22,0x7d,0x71,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1717d22 <unknown> + +bfmla za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h // 11000001-01111011-00111101-10000111 +// CHECK-INST: bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h +// CHECK-ENCODING: [0x87,0x3d,0x7b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17b3d87 <unknown> + +bfmla za.h[w9, 7], {z12.h - z15.h}, z11.h // 11000001-01111011-00111101-10000111 +// CHECK-INST: bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h +// CHECK-ENCODING: [0x87,0x3d,0x7b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17b3d87 <unknown> + +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] +// CHECK-ENCODING: [0x20,0x90,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109020 <unknown> + +bfmla za.h[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] +// CHECK-ENCODING: [0x20,0x90,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109020 <unknown> + +bfmla za.h[w10, 5, vgx4], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00100101 +// CHECK-INST: bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] +// CHECK-ENCODING: [0x25,0xd5,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c115d525 <unknown> + +bfmla za.h[w10, 5], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00100101 +// CHECK-INST: bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] +// CHECK-ENCODING: [0x25,0xd5,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c115d525 <unknown> + +bfmla za.h[w11, 7, vgx4], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] +// CHECK-ENCODING: [0xa7,0xfd,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c118fda7 <unknown> + +bfmla za.h[w11, 7], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10100111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] +// CHECK-ENCODING: [0xa7,0xfd,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c118fda7 <unknown> + +bfmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10101111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] +// CHECK-ENCODING: [0xaf,0xff,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11fffaf <unknown> + +bfmla za.h[w11, 7], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10101111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] +// CHECK-ENCODING: [0xaf,0xff,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11fffaf <unknown> + +bfmla za.h[w8, 5, vgx4], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] +// CHECK-ENCODING: [0x25,0x9e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109e25 <unknown> + +bfmla za.h[w8, 5], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00100101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] +// CHECK-ENCODING: [0x25,0x9e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109e25 <unknown> + +bfmla za.h[w8, 1, vgx4], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] +// CHECK-ENCODING: [0x21,0x94,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9421 <unknown> + +bfmla za.h[w8, 1], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00100001 +// CHECK-INST: bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] +// CHECK-ENCODING: [0x21,0x94,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9421 <unknown> + +bfmla za.h[w10, 0, vgx4], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00101000 +// CHECK-INST: bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] +// CHECK-ENCODING: [0x28,0xd6,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c114d628 <unknown> + +bfmla za.h[w10, 0], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00101000 +// CHECK-INST: bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] +// CHECK-ENCODING: [0x28,0xd6,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c114d628 <unknown> + +bfmla za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] +// CHECK-ENCODING: [0xa0,0x99,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11299a0 <unknown> + +bfmla za.h[w8, 0], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10100000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] +// CHECK-ENCODING: [0xa0,0x99,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11299a0 <unknown> + +bfmla za.h[w10, 1, vgx4], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] +// CHECK-ENCODING: [0x21,0xd8,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11ad821 <unknown> + +bfmla za.h[w10, 1], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00100001 +// CHECK-INST: bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] +// CHECK-ENCODING: [0x21,0xd8,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11ad821 <unknown> + +bfmla za.h[w8, 5, vgx4], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10101101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] +// CHECK-ENCODING: [0xad,0x9a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9aad <unknown> + +bfmla za.h[w8, 5], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10101101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] +// CHECK-ENCODING: [0xad,0x9a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9aad <unknown> + +bfmla za.h[w11, 2, vgx4], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] +// CHECK-ENCODING: [0x22,0xf5,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c111f522 <unknown> + +bfmla za.h[w11, 2], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00100010 +// CHECK-INST: bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] +// CHECK-ENCODING: [0x22,0xf5,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c111f522 <unknown> + +bfmla za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10100111 +// CHECK-INST: bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] +// CHECK-ENCODING: [0xa7,0xb9,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11bb9a7 <unknown> + +bfmla za.h[w9, 7], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10100111 +// CHECK-INST: bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] +// CHECK-ENCODING: [0xa7,0xb9,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11bb9a7 <unknown> + +bfmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-11100001-00010000-00001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x08,0x10,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11008 <unknown> + +bfmla za.h[w8, 0], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-11100001-00010000-00001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x08,0x10,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11008 <unknown> + +bfmla za.h[w10, 5, vgx4], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-11110101-01010001-00001101 +// CHECK-INST: bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x0d,0x51,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f5510d <unknown> + +bfmla za.h[w10, 5], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-11110101-01010001-00001101 +// CHECK-INST: bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x0d,0x51,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f5510d <unknown> + +bfmla za.h[w11, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-01110001-10001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x8f,0x71,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9718f <unknown> + +bfmla za.h[w11, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-01110001-10001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x8f,0x71,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9718f <unknown> + +bfmla za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-11111101-01110011-10001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x8f,0x73,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd738f <unknown> + +bfmla za.h[w11, 7], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-11111101-01110011-10001111 +// CHECK-INST: bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x8f,0x73,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd738f <unknown> + +bfmla za.h[w8, 5, vgx4], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-11110001-00010010-00001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } +// CHECK-ENCODING: [0x0d,0x12,0xf1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f1120d <unknown> + +bfmla za.h[w8, 5], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-11110001-00010010-00001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } +// CHECK-ENCODING: [0x0d,0x12,0xf1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f1120d <unknown> + +bfmla za.h[w8, 1, vgx4], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-11111101-00010000-00001001 +// CHECK-INST: bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x09,0x10,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd1009 <unknown> + +bfmla za.h[w8, 1], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-11111101-00010000-00001001 +// CHECK-INST: bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x09,0x10,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd1009 <unknown> + +bfmla za.h[w10, 0, vgx4], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-11110101-01010010-00001000 +// CHECK-INST: bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x08,0x52,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f55208 <unknown> + +bfmla za.h[w10, 0], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-11110101-01010010-00001000 +// CHECK-INST: bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x08,0x52,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f55208 <unknown> + +bfmla za.h[w8, 0, vgx4], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-11100001-00010001-10001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x88,0x11,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11188 <unknown> + +bfmla za.h[w8, 0], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-11100001-00010001-10001000 +// CHECK-INST: bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x88,0x11,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11188 <unknown> + +bfmla za.h[w10, 1, vgx4], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-11111001-01010000-00001001 +// CHECK-INST: bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } +// CHECK-ENCODING: [0x09,0x50,0xf9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f95009 <unknown> + +bfmla za.h[w10, 1], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-11111001-01010000-00001001 +// CHECK-INST: bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } +// CHECK-ENCODING: [0x09,0x50,0xf9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f95009 <unknown> + +bfmla za.h[w8, 5, vgx4], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-11111101-00010010-10001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x8d,0x12,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd128d <unknown> + +bfmla za.h[w8, 5], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-11111101-00010010-10001101 +// CHECK-INST: bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x8d,0x12,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd128d <unknown> + +bfmla za.h[w11, 2, vgx4], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-11100001-01110001-00001010 +// CHECK-INST: bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x0a,0x71,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e1710a <unknown> + +bfmla za.h[w11, 2], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-11100001-01110001-00001010 +// CHECK-INST: bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x0a,0x71,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e1710a <unknown> + +bfmla za.h[w9, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-00110001-10001111 +// CHECK-INST: bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x8f,0x31,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9318f <unknown> + +bfmla za.h[w9, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-00110001-10001111 +// CHECK-INST: bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x8f,0x31,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9318f <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfmls-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmls-diagnostics.s new file mode 100644 index 0000000..d6e7713 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmls-diagnostics.s @@ -0,0 +1,94 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: bfmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: bfmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid indexed-vector or single-vector register + +bfmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w8, 1], {z0.h-z3.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: bfmls za.h[w8, 1], {z0.h-z3.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector select register + +bfmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector select offset + +bfmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +bfmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h +// CHECK-NEXT: bfmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector lane index + +bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmls.s b/llvm/test/MC/AArch64/SME2/bfmls.s new file mode 100644 index 0000000..8d5bdc4 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmls.s @@ -0,0 +1,876 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmls za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h // 11000001-01100000-00011100-00001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x08,0x1c,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601c08 <unknown> + +bfmls za.h[w8, 0], {z0.h - z1.h}, z0.h // 11000001-01100000-00011100-00001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x08,0x1c,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601c08 <unknown> + +bfmls za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h // 11000001-01100101-01011101-01001101 +// CHECK-INST: bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h +// CHECK-ENCODING: [0x4d,0x5d,0x65,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1655d4d <unknown> + +bfmls za.h[w10, 5], {z10.h - z11.h}, z5.h // 11000001-01100101-01011101-01001101 +// CHECK-INST: bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h +// CHECK-ENCODING: [0x4d,0x5d,0x65,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1655d4d <unknown> + +bfmls za.h[w11, 7, vgx2], {z13.h, z14.h}, z8.h // 11000001-01101000-01111101-10101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h +// CHECK-ENCODING: [0xaf,0x7d,0x68,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1687daf <unknown> + +bfmls za.h[w11, 7], {z13.h - z14.h}, z8.h // 11000001-01101000-01111101-10101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h +// CHECK-ENCODING: [0xaf,0x7d,0x68,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1687daf <unknown> + +bfmls za.h[w11, 7, vgx2], {z31.h, z0.h}, z15.h // 11000001-01101111-01111111-11101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h +// CHECK-ENCODING: [0xef,0x7f,0x6f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16f7fef <unknown> + +bfmls za.h[w11, 7], {z31.h - z0.h}, z15.h // 11000001-01101111-01111111-11101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h +// CHECK-ENCODING: [0xef,0x7f,0x6f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16f7fef <unknown> + +bfmls za.h[w8, 5, vgx2], {z17.h, z18.h}, z0.h // 11000001-01100000-00011110-00101101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h +// CHECK-ENCODING: [0x2d,0x1e,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601e2d <unknown> + +bfmls za.h[w8, 5], {z17.h - z18.h}, z0.h // 11000001-01100000-00011110-00101101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h +// CHECK-ENCODING: [0x2d,0x1e,0x60,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1601e2d <unknown> + +bfmls za.h[w8, 1, vgx2], {z1.h, z2.h}, z14.h // 11000001-01101110-00011100-00101001 +// CHECK-INST: bfmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h +// CHECK-ENCODING: [0x29,0x1c,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1c29 <unknown> + +bfmls za.h[w8, 1], {z1.h - z2.h}, z14.h // 11000001-01101110-00011100-00101001 +// CHECK-INST: bfmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h +// CHECK-ENCODING: [0x29,0x1c,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1c29 <unknown> + +bfmls za.h[w10, 0, vgx2], {z19.h, z20.h}, z4.h // 11000001-01100100-01011110-01101000 +// CHECK-INST: bfmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h +// CHECK-ENCODING: [0x68,0x5e,0x64,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1645e68 <unknown> + +bfmls za.h[w10, 0], {z19.h - z20.h}, z4.h // 11000001-01100100-01011110-01101000 +// CHECK-INST: bfmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h +// CHECK-ENCODING: [0x68,0x5e,0x64,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1645e68 <unknown> + +bfmls za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h // 11000001-01100010-00011101-10001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h +// CHECK-ENCODING: [0x88,0x1d,0x62,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1621d88 <unknown> + +bfmls za.h[w8, 0], {z12.h - z13.h}, z2.h // 11000001-01100010-00011101-10001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h +// CHECK-ENCODING: [0x88,0x1d,0x62,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1621d88 <unknown> + +bfmls za.h[w10, 1, vgx2], {z1.h, z2.h}, z10.h // 11000001-01101010-01011100-00101001 +// CHECK-INST: bfmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h +// CHECK-ENCODING: [0x29,0x5c,0x6a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16a5c29 <unknown> + +bfmls za.h[w10, 1], {z1.h - z2.h}, z10.h // 11000001-01101010-01011100-00101001 +// CHECK-INST: bfmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h +// CHECK-ENCODING: [0x29,0x5c,0x6a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16a5c29 <unknown> + +bfmls za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h // 11000001-01101110-00011110-11001101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h +// CHECK-ENCODING: [0xcd,0x1e,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1ecd <unknown> + +bfmls za.h[w8, 5], {z22.h - z23.h}, z14.h // 11000001-01101110-00011110-11001101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h +// CHECK-ENCODING: [0xcd,0x1e,0x6e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16e1ecd <unknown> + +bfmls za.h[w11, 2, vgx2], {z9.h, z10.h}, z1.h // 11000001-01100001-01111101-00101010 +// CHECK-INST: bfmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h +// CHECK-ENCODING: [0x2a,0x7d,0x61,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1617d2a <unknown> + +bfmls za.h[w11, 2], {z9.h - z10.h}, z1.h // 11000001-01100001-01111101-00101010 +// CHECK-INST: bfmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h +// CHECK-ENCODING: [0x2a,0x7d,0x61,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1617d2a <unknown> + +bfmls za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h // 11000001-01101011-00111101-10001111 +// CHECK-INST: bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h +// CHECK-ENCODING: [0x8f,0x3d,0x6b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16b3d8f <unknown> + +bfmls za.h[w9, 7], {z12.h - z13.h}, z11.h // 11000001-01101011-00111101-10001111 +// CHECK-INST: bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h +// CHECK-ENCODING: [0x8f,0x3d,0x6b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c16b3d8f <unknown> + +bfmls za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-00010000-00010000-00110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] +// CHECK-ENCODING: [0x30,0x10,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101030 <unknown> + +bfmls za.h[w8, 0], {z0.h - z1.h}, z0.h[0] // 11000001-00010000-00010000-00110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] +// CHECK-ENCODING: [0x30,0x10,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101030 <unknown> + +bfmls za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h[2] // 11000001-00010101-01010101-01110101 +// CHECK-INST: bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] +// CHECK-ENCODING: [0x75,0x55,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1155575 <unknown> + +bfmls za.h[w10, 5], {z10.h - z11.h}, z5.h[2] // 11000001-00010101-01010101-01110101 +// CHECK-INST: bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] +// CHECK-ENCODING: [0x75,0x55,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1155575 <unknown> + +bfmls za.h[w11, 7, vgx2], {z12.h, z13.h}, z8.h[6] // 11000001-00011000-01111101-10110111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] +// CHECK-ENCODING: [0xb7,0x7d,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1187db7 <unknown> + +bfmls za.h[w11, 7], {z12.h - z13.h}, z8.h[6] // 11000001-00011000-01111101-10110111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] +// CHECK-ENCODING: [0xb7,0x7d,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1187db7 <unknown> + +bfmls za.h[w11, 7, vgx2], {z30.h, z31.h}, z15.h[7] // 11000001-00011111-01111111-11111111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11f7fff <unknown> + +bfmls za.h[w11, 7], {z30.h - z31.h}, z15.h[7] // 11000001-00011111-01111111-11111111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11f7fff <unknown> + +bfmls za.h[w8, 5, vgx2], {z16.h, z17.h}, z0.h[6] // 11000001-00010000-00011110-00110101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] +// CHECK-ENCODING: [0x35,0x1e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101e35 <unknown> + +bfmls za.h[w8, 5], {z16.h - z17.h}, z0.h[6] // 11000001-00010000-00011110-00110101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] +// CHECK-ENCODING: [0x35,0x1e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1101e35 <unknown> + +bfmls za.h[w8, 1, vgx2], {z0.h, z1.h}, z14.h[2] // 11000001-00011110-00010100-00110001 +// CHECK-INST: bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] +// CHECK-ENCODING: [0x31,0x14,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1431 <unknown> + +bfmls za.h[w8, 1], {z0.h - z1.h}, z14.h[2] // 11000001-00011110-00010100-00110001 +// CHECK-INST: bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] +// CHECK-ENCODING: [0x31,0x14,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1431 <unknown> + +bfmls za.h[w10, 0, vgx2], {z18.h, z19.h}, z4.h[3] // 11000001-00010100-01010110-01111000 +// CHECK-INST: bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] +// CHECK-ENCODING: [0x78,0x56,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1145678 <unknown> + +bfmls za.h[w10, 0], {z18.h - z19.h}, z4.h[3] // 11000001-00010100-01010110-01111000 +// CHECK-INST: bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] +// CHECK-ENCODING: [0x78,0x56,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1145678 <unknown> + +bfmls za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h[4] // 11000001-00010010-00011001-10110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] +// CHECK-ENCODING: [0xb0,0x19,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11219b0 <unknown> + +bfmls za.h[w8, 0], {z12.h - z13.h}, z2.h[4] // 11000001-00010010-00011001-10110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] +// CHECK-ENCODING: [0xb0,0x19,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11219b0 <unknown> + +bfmls za.h[w10, 1, vgx2], {z0.h, z1.h}, z10.h[4] // 11000001-00011010-01011000-00110001 +// CHECK-INST: bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] +// CHECK-ENCODING: [0x31,0x58,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11a5831 <unknown> + +bfmls za.h[w10, 1], {z0.h - z1.h}, z10.h[4] // 11000001-00011010-01011000-00110001 +// CHECK-INST: bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] +// CHECK-ENCODING: [0x31,0x58,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11a5831 <unknown> + +bfmls za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h[5] // 11000001-00011110-00011010-11111101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] +// CHECK-ENCODING: [0xfd,0x1a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1afd <unknown> + +bfmls za.h[w8, 5], {z22.h - z23.h}, z14.h[5] // 11000001-00011110-00011010-11111101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] +// CHECK-ENCODING: [0xfd,0x1a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e1afd <unknown> + +bfmls za.h[w11, 2, vgx2], {z8.h, z9.h}, z1.h[2] // 11000001-00010001-01110101-00110010 +// CHECK-INST: bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] +// CHECK-ENCODING: [0x32,0x75,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1117532 <unknown> + +bfmls za.h[w11, 2], {z8.h - z9.h}, z1.h[2] // 11000001-00010001-01110101-00110010 +// CHECK-INST: bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] +// CHECK-ENCODING: [0x32,0x75,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1117532 <unknown> + +bfmls za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h[4] // 11000001-00011011-00111001-10110111 +// CHECK-INST: bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] +// CHECK-ENCODING: [0xb7,0x39,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11b39b7 <unknown> + +bfmls za.h[w9, 7], {z12.h - z13.h}, z11.h[4] // 11000001-00011011-00111001-10110111 +// CHECK-INST: bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] +// CHECK-ENCODING: [0xb7,0x39,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11b39b7 <unknown> + +bfmls za.h[w8, 0, vgx2], {z0.h, z1.h}, {z0.h, z1.h} // 11000001, 11100000-00010000-00011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x18,0x10,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e01018 <unknown> + +bfmls za.h[w8, 0], {z0.h - z1.h}, {z0.h - z1.h} // 11000001-11100000-00010000-00011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x18,0x10,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e01018 <unknown> + +bfmls za.h[w10, 5, vgx2], {z10.h, z11.h}, {z20.h, z21.h} // 11000001, 11110100-01010001-01011101 +// CHECK-INST: bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x51,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f4515d <unknown> + +bfmls za.h[w10, 5], {z10.h - z11.h}, {z20.h - z21.h} // 11000001-11110100-01010001-01011101 +// CHECK-INST: bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x5d,0x51,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f4515d <unknown> + +bfmls za.h[w11, 7, vgx2], {z12.h, z13.h}, {z8.h, z9.h} // 11000001, 11101000-01110001-10011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x9f,0x71,0xe8,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e8719f <unknown> + +bfmls za.h[w11, 7], {z12.h - z13.h}, {z8.h - z9.h} // 11000001-11101000-01110001-10011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x9f,0x71,0xe8,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e8719f <unknown> + +bfmls za.h[w11, 7, vgx2], {z30.h, z31.h}, {z30.h, z31.h} // 11000001, 11111110-01110011-11011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x73,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe73df <unknown> + +bfmls za.h[w11, 7], {z30.h - z31.h}, {z30.h - z31.h} // 11000001-11111110-01110011-11011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdf,0x73,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe73df <unknown> + +bfmls za.h[w8, 5, vgx2], {z16.h, z17.h}, {z16.h, z17.h} // 11000001, 11110000-00010010-00011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x1d,0x12,0xf0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f0121d <unknown> + +bfmls za.h[w8, 5], {z16.h - z17.h}, {z16.h - z17.h} // 11000001-11110000-00010010-00011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x1d,0x12,0xf0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f0121d <unknown> + +bfmls za.h[w8, 1, vgx2], {z0.h, z1.h}, {z30.h, z31.h} // 11000001, 11111110-00010000-00011001 +// CHECK-INST: bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x19,0x10,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe1019 <unknown> + +bfmls za.h[w8, 1], {z0.h - z1.h}, {z30.h - z31.h} // 11000001-11111110-00010000-00011001 +// CHECK-INST: bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x19,0x10,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe1019 <unknown> + +bfmls za.h[w10, 0, vgx2], {z18.h, z19.h}, {z20.h, z21.h} // 11000001, 11110100-01010010-01011000 +// CHECK-INST: bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x58,0x52,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f45258 <unknown> + +bfmls za.h[w10, 0], {z18.h - z19.h}, {z20.h - z21.h} // 11000001-11110100-01010010-01011000 +// CHECK-INST: bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x58,0x52,0xf4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f45258 <unknown> + +bfmls za.h[w8, 0, vgx2], {z12.h, z13.h}, {z2.h, z3.h} // 11000001, 11100010-00010001-10011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } +// CHECK-ENCODING: [0x98,0x11,0xe2,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e21198 <unknown> + +bfmls za.h[w8, 0], {z12.h - z13.h}, {z2.h - z3.h} // 11000001-11100010-00010001-10011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } +// CHECK-ENCODING: [0x98,0x11,0xe2,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e21198 <unknown> + +bfmls za.h[w10, 1, vgx2], {z0.h, z1.h}, {z26.h, z27.h} // 11000001, 11111010-01010000-00011001 +// CHECK-INST: bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } +// CHECK-ENCODING: [0x19,0x50,0xfa,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fa5019 <unknown> + +bfmls za.h[w10, 1], {z0.h - z1.h}, {z26.h - z27.h} // 11000001-11111010-01010000-00011001 +// CHECK-INST: bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } +// CHECK-ENCODING: [0x19,0x50,0xfa,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fa5019 <unknown> + +bfmls za.h[w8, 5, vgx2], {z22.h, z23.h}, {z30.h, z31.h} // 11000001, 11111110-00010010-11011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdd,0x12,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe12dd <unknown> + +bfmls za.h[w8, 5], {z22.h - z23.h}, {z30.h - z31.h} // 11000001-11111110-00010010-11011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xdd,0x12,0xfe,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fe12dd <unknown> + +bfmls za.h[w11, 2, vgx2], {z8.h, z9.h}, {z0.h, z1.h} // 11000001, 11100000-01110001-00011010 +// CHECK-INST: bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x1a,0x71,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e0711a <unknown> + +bfmls za.h[w11, 2], {z8.h - z9.h}, {z0.h - z1.h} // 11000001-11100000-01110001-00011010 +// CHECK-INST: bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x1a,0x71,0xe0,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e0711a <unknown> + +bfmls za.h[w9, 7, vgx2], {z12.h, z13.h}, {z10.h, z11.h} // 11000001, 11101010-00110001-10011111 +// CHECK-INST: bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } +// CHECK-ENCODING: [0x9f,0x31,0xea,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1ea319f <unknown> + +bfmls za.h[w9, 7], {z12.h - z13.h}, {z10.h - z11.h} // 11000001-11101010-00110001-10011111 +// CHECK-INST: bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } +// CHECK-ENCODING: [0x9f,0x31,0xea,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1ea319f <unknown> + +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h // 11000001-01110000-00011100-00001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x08,0x1c,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701c08 <unknown> + +bfmls za.h[w8, 0], {z0.h - z3.h}, z0.h // 11000001-01110000-00011100-00001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x08,0x1c,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701c08 <unknown> + +bfmls za.h[w10, 5, vgx4], {z10.h - z13.h}, z5.h // 11000001-01110101-01011101-01001101 +// CHECK-INST: bfmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h +// CHECK-ENCODING: [0x4d,0x5d,0x75,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1755d4d <unknown> + +bfmls za.h[w10, 5], {z10.h - z13.h}, z5.h // 11000001-01110101-01011101-01001101 +// CHECK-INST: bfmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h +// CHECK-ENCODING: [0x4d,0x5d,0x75,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1755d4d <unknown> + +bfmls za.h[w11, 7, vgx4], {z13.h - z16.h}, z8.h // 11000001-01111000-01111101-10101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h +// CHECK-ENCODING: [0xaf,0x7d,0x78,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1787daf <unknown> + +bfmls za.h[w11, 7], {z13.h - z16.h}, z8.h // 11000001-01111000-01111101-10101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h +// CHECK-ENCODING: [0xaf,0x7d,0x78,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1787daf <unknown> + +bfmls za.h[w11, 7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-01111111-01111111-11101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h +// CHECK-ENCODING: [0xef,0x7f,0x7f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17f7fef <unknown> + +bfmls za.h[w11, 7], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-01111111-01111111-11101111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h +// CHECK-ENCODING: [0xef,0x7f,0x7f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17f7fef <unknown> + +bfmls za.h[w8, 5, vgx4], {z17.h - z20.h}, z0.h // 11000001-01110000-00011110-00101101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h +// CHECK-ENCODING: [0x2d,0x1e,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701e2d <unknown> + +bfmls za.h[w8, 5], {z17.h - z20.h}, z0.h // 11000001-01110000-00011110-00101101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h +// CHECK-ENCODING: [0x2d,0x1e,0x70,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1701e2d <unknown> + +bfmls za.h[w8, 1, vgx4], {z1.h - z4.h}, z14.h // 11000001-01111110-00011100-00101001 +// CHECK-INST: bfmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h +// CHECK-ENCODING: [0x29,0x1c,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1c29 <unknown> + +bfmls za.h[w8, 1], {z1.h - z4.h}, z14.h // 11000001-01111110-00011100-00101001 +// CHECK-INST: bfmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h +// CHECK-ENCODING: [0x29,0x1c,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1c29 <unknown> + +bfmls za.h[w10, 0, vgx4], {z19.h - z22.h}, z4.h // 11000001-01110100-01011110-01101000 +// CHECK-INST: bfmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h +// CHECK-ENCODING: [0x68,0x5e,0x74,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1745e68 <unknown> + +bfmls za.h[w10, 0], {z19.h - z22.h}, z4.h // 11000001-01110100-01011110-01101000 +// CHECK-INST: bfmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h +// CHECK-ENCODING: [0x68,0x5e,0x74,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1745e68 <unknown> + +bfmls za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h // 11000001-01110010-00011101-10001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h +// CHECK-ENCODING: [0x88,0x1d,0x72,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1721d88 <unknown> + +bfmls za.h[w8, 0], {z12.h - z15.h}, z2.h // 11000001-01110010-00011101-10001000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h +// CHECK-ENCODING: [0x88,0x1d,0x72,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1721d88 <unknown> + +bfmls za.h[w10, 1, vgx4], {z1.h - z4.h}, z10.h // 11000001-01111010-01011100-00101001 +// CHECK-INST: bfmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h +// CHECK-ENCODING: [0x29,0x5c,0x7a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17a5c29 <unknown> + +bfmls za.h[w10, 1], {z1.h - z4.h}, z10.h // 11000001-01111010-01011100-00101001 +// CHECK-INST: bfmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h +// CHECK-ENCODING: [0x29,0x5c,0x7a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17a5c29 <unknown> + +bfmls za.h[w8, 5, vgx4], {z22.h - z25.h}, z14.h // 11000001-01111110-00011110-11001101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h +// CHECK-ENCODING: [0xcd,0x1e,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1ecd <unknown> + +bfmls za.h[w8, 5], {z22.h - z25.h}, z14.h // 11000001-01111110-00011110-11001101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h +// CHECK-ENCODING: [0xcd,0x1e,0x7e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17e1ecd <unknown> + +bfmls za.h[w11, 2, vgx4], {z9.h - z12.h}, z1.h // 11000001-01110001-01111101-00101010 +// CHECK-INST: bfmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h +// CHECK-ENCODING: [0x2a,0x7d,0x71,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1717d2a <unknown> + +bfmls za.h[w11, 2], {z9.h - z12.h}, z1.h // 11000001-01110001-01111101-00101010 +// CHECK-INST: bfmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h +// CHECK-ENCODING: [0x2a,0x7d,0x71,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1717d2a <unknown> + +bfmls za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h // 11000001-01111011-00111101-10001111 +// CHECK-INST: bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h +// CHECK-ENCODING: [0x8f,0x3d,0x7b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17b3d8f <unknown> + +bfmls za.h[w9, 7], {z12.h - z15.h}, z11.h // 11000001-01111011-00111101-10001111 +// CHECK-INST: bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h +// CHECK-ENCODING: [0x8f,0x3d,0x7b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c17b3d8f <unknown> + +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] +// CHECK-ENCODING: [0x30,0x90,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109030 <unknown> + +bfmls za.h[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] +// CHECK-ENCODING: [0x30,0x90,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109030 <unknown> + +bfmls za.h[w10, 5, vgx4], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00110101 +// CHECK-INST: bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] +// CHECK-ENCODING: [0x35,0xd5,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c115d535 <unknown> + +bfmls za.h[w10, 5], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00110101 +// CHECK-INST: bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] +// CHECK-ENCODING: [0x35,0xd5,0x15,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c115d535 <unknown> + +bfmls za.h[w11, 7, vgx4], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10110111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] +// CHECK-ENCODING: [0xb7,0xfd,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c118fdb7 <unknown> + +bfmls za.h[w11, 7], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10110111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] +// CHECK-ENCODING: [0xb7,0xfd,0x18,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c118fdb7 <unknown> + +bfmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10111111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] +// CHECK-ENCODING: [0xbf,0xff,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11fffbf <unknown> + +bfmls za.h[w11, 7], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10111111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] +// CHECK-ENCODING: [0xbf,0xff,0x1f,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11fffbf <unknown> + +bfmls za.h[w8, 5, vgx4], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00110101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] +// CHECK-ENCODING: [0x35,0x9e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109e35 <unknown> + +bfmls za.h[w8, 5], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00110101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] +// CHECK-ENCODING: [0x35,0x9e,0x10,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1109e35 <unknown> + +bfmls za.h[w8, 1, vgx4], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00110001 +// CHECK-INST: bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] +// CHECK-ENCODING: [0x31,0x94,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9431 <unknown> + +bfmls za.h[w8, 1], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00110001 +// CHECK-INST: bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] +// CHECK-ENCODING: [0x31,0x94,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9431 <unknown> + +bfmls za.h[w10, 0, vgx4], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00111000 +// CHECK-INST: bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] +// CHECK-ENCODING: [0x38,0xd6,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c114d638 <unknown> + +bfmls za.h[w10, 0], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00111000 +// CHECK-INST: bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] +// CHECK-ENCODING: [0x38,0xd6,0x14,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c114d638 <unknown> + +bfmls za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] +// CHECK-ENCODING: [0xb0,0x99,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11299b0 <unknown> + +bfmls za.h[w8, 0], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10110000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] +// CHECK-ENCODING: [0xb0,0x99,0x12,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11299b0 <unknown> + +bfmls za.h[w10, 1, vgx4], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00110001 +// CHECK-INST: bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] +// CHECK-ENCODING: [0x31,0xd8,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11ad831 <unknown> + +bfmls za.h[w10, 1], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00110001 +// CHECK-INST: bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] +// CHECK-ENCODING: [0x31,0xd8,0x1a,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11ad831 <unknown> + +bfmls za.h[w8, 5, vgx4], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10111101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] +// CHECK-ENCODING: [0xbd,0x9a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9abd <unknown> + +bfmls za.h[w8, 5], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10111101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] +// CHECK-ENCODING: [0xbd,0x9a,0x1e,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11e9abd <unknown> + +bfmls za.h[w11, 2, vgx4], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00110010 +// CHECK-INST: bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] +// CHECK-ENCODING: [0x32,0xf5,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c111f532 <unknown> + +bfmls za.h[w11, 2], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00110010 +// CHECK-INST: bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] +// CHECK-ENCODING: [0x32,0xf5,0x11,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c111f532 <unknown> + +bfmls za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10110111 +// CHECK-INST: bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] +// CHECK-ENCODING: [0xb7,0xb9,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11bb9b7 <unknown> + +bfmls za.h[w9, 7], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10110111 +// CHECK-INST: bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] +// CHECK-ENCODING: [0xb7,0xb9,0x1b,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c11bb9b7 <unknown> + +bfmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-11100001-00010000-00011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x18,0x10,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11018 <unknown> + +bfmls za.h[w8, 0], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-11100001-00010000-00011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x18,0x10,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11018 <unknown> + +bfmls za.h[w10, 5, vgx4], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-11110101-01010001-00011101 +// CHECK-INST: bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x1d,0x51,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f5511d <unknown> + +bfmls za.h[w10, 5], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-11110101-01010001-00011101 +// CHECK-INST: bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x1d,0x51,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f5511d <unknown> + +bfmls za.h[w11, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-01110001-10011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x9f,0x71,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9719f <unknown> + +bfmls za.h[w11, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-01110001-10011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x9f,0x71,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9719f <unknown> + +bfmls za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-11111101-01110011-10011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x9f,0x73,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd739f <unknown> + +bfmls za.h[w11, 7], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-11111101-01110011-10011111 +// CHECK-INST: bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x9f,0x73,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd739f <unknown> + +bfmls za.h[w8, 5, vgx4], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-11110001-00010010-00011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } +// CHECK-ENCODING: [0x1d,0x12,0xf1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f1121d <unknown> + +bfmls za.h[w8, 5], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-11110001-00010010-00011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } +// CHECK-ENCODING: [0x1d,0x12,0xf1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f1121d <unknown> + +bfmls za.h[w8, 1, vgx4], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-11111101-00010000-00011001 +// CHECK-INST: bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x19,0x10,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd1019 <unknown> + +bfmls za.h[w8, 1], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-11111101-00010000-00011001 +// CHECK-INST: bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x19,0x10,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd1019 <unknown> + +bfmls za.h[w10, 0, vgx4], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-11110101-01010010-00011000 +// CHECK-INST: bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x18,0x52,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f55218 <unknown> + +bfmls za.h[w10, 0], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-11110101-01010010-00011000 +// CHECK-INST: bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x18,0x52,0xf5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f55218 <unknown> + +bfmls za.h[w8, 0, vgx4], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-11100001-00010001-10011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x98,0x11,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11198 <unknown> + +bfmls za.h[w8, 0], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-11100001-00010001-10011000 +// CHECK-INST: bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x98,0x11,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e11198 <unknown> + +bfmls za.h[w10, 1, vgx4], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-11111001-01010000-00011001 +// CHECK-INST: bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } +// CHECK-ENCODING: [0x19,0x50,0xf9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f95019 <unknown> + +bfmls za.h[w10, 1], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-11111001-01010000-00011001 +// CHECK-INST: bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } +// CHECK-ENCODING: [0x19,0x50,0xf9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1f95019 <unknown> + +bfmls za.h[w8, 5, vgx4], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-11111101-00010010-10011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x9d,0x12,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd129d <unknown> + +bfmls za.h[w8, 5], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-11111101-00010010-10011101 +// CHECK-INST: bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x9d,0x12,0xfd,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1fd129d <unknown> + +bfmls za.h[w11, 2, vgx4], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-11100001-01110001-00011010 +// CHECK-INST: bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x1a,0x71,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e1711a <unknown> + +bfmls za.h[w11, 2], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-11100001-01110001-00011010 +// CHECK-INST: bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x1a,0x71,0xe1,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e1711a <unknown> + +bfmls za.h[w9, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-00110001-10011111 +// CHECK-INST: bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x9f,0x31,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9319f <unknown> + +bfmls za.h[w9, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-11101001-00110001-10011111 +// CHECK-INST: bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x9f,0x31,0xe9,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e9319f <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfmopa-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmopa-diagnostics.s new file mode 100644 index 0000000..e6d208d --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmopa-diagnostics.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +bfmopa za1.h, p8/m, p5/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfmopa za1.h, p8/m, p5/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmopa za1.h, p5/m, p8/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfmopa za1.h, p5/m, p8/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmopa za1.h, p5.h, p5/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfmopa za1.h, p5.h, p5/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid matrix operand + +bfmopa za2.h, p5/m, p5/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmopa za2.h, p5/m, p5/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid register suffixes + +bfmopa za1.h, p5/m, p5/m, z12.h, z11.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmopa za1.h, p5/m, p5/m, z12.h, z11.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmopa.s b/llvm/test/MC/AArch64/SME2/bfmopa.s new file mode 100644 index 0000000..2a9b1e5 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmopa.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmopa za0.h, p0/m, p0/m, z0.h, z0.h // 10000001-10100000-00000000-00001000 +// CHECK-INST: bfmopa za0.h, p0/m, p0/m, z0.h, z0.h +// CHECK-ENCODING: [0x08,0x00,0xa0,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a00008 <unknown> + +bfmopa za1.h, p5/m, p2/m, z10.h, z21.h // 10000001-10110101-01010101-01001001 +// CHECK-INST: bfmopa za1.h, p5/m, p2/m, z10.h, z21.h +// CHECK-ENCODING: [0x49,0x55,0xb5,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81b55549 <unknown> + +bfmopa za1.h, p3/m, p7/m, z13.h, z8.h // 10000001-10101000-11101101-10101001 +// CHECK-INST: bfmopa za1.h, p3/m, p7/m, z13.h, z8.h +// CHECK-ENCODING: [0xa9,0xed,0xa8,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a8eda9 <unknown> + +bfmopa za1.h, p7/m, p7/m, z31.h, z31.h // 10000001-10111111-11111111-11101001 +// CHECK-INST: bfmopa za1.h, p7/m, p7/m, z31.h, z31.h +// CHECK-ENCODING: [0xe9,0xff,0xbf,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81bfffe9 <unknown> + +bfmopa za1.h, p3/m, p0/m, z17.h, z16.h // 10000001-10110000-00001110-00101001 +// CHECK-INST: bfmopa za1.h, p3/m, p0/m, z17.h, z16.h +// CHECK-ENCODING: [0x29,0x0e,0xb0,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81b00e29 <unknown> + +bfmopa za1.h, p1/m, p4/m, z1.h, z30.h // 10000001-10111110-10000100-00101001 +// CHECK-INST: bfmopa za1.h, p1/m, p4/m, z1.h, z30.h +// CHECK-ENCODING: [0x29,0x84,0xbe,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81be8429 <unknown> + +bfmopa za0.h, p5/m, p2/m, z19.h, z20.h // 10000001-10110100-01010110-01101000 +// CHECK-INST: bfmopa za0.h, p5/m, p2/m, z19.h, z20.h +// CHECK-ENCODING: [0x68,0x56,0xb4,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81b45668 <unknown> + +bfmopa za0.h, p6/m, p0/m, z12.h, z2.h // 10000001-10100010-00011001-10001000 +// CHECK-INST: bfmopa za0.h, p6/m, p0/m, z12.h, z2.h +// CHECK-ENCODING: [0x88,0x19,0xa2,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a21988 <unknown> + +bfmopa za1.h, p2/m, p6/m, z1.h, z26.h // 10000001-10111010-11001000-00101001 +// CHECK-INST: bfmopa za1.h, p2/m, p6/m, z1.h, z26.h +// CHECK-ENCODING: [0x29,0xc8,0xba,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81bac829 <unknown> + +bfmopa za1.h, p2/m, p0/m, z22.h, z30.h // 10000001-10111110-00001010-11001001 +// CHECK-INST: bfmopa za1.h, p2/m, p0/m, z22.h, z30.h +// CHECK-ENCODING: [0xc9,0x0a,0xbe,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81be0ac9 <unknown> + +bfmopa za0.h, p5/m, p7/m, z9.h, z1.h // 10000001-10100001-11110101-00101000 +// CHECK-INST: bfmopa za0.h, p5/m, p7/m, z9.h, z1.h +// CHECK-ENCODING: [0x28,0xf5,0xa1,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a1f528 <unknown> + +bfmopa za1.h, p2/m, p5/m, z12.h, z11.h // 10000001-10101011-10101001-10001001 +// CHECK-INST: bfmopa za1.h, p2/m, p5/m, z12.h, z11.h +// CHECK-ENCODING: [0x89,0xa9,0xab,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81aba989 <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfmops-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfmops-diagnostics.s new file mode 100644 index 0000000..14c25de --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmops-diagnostics.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +bfmops za1.h, p8/m, p5/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfmops za1.h, p8/m, p5/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmops za1.h, p5/m, p8/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfmops za1.h, p5/m, p8/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfmops za1.h, p5.h, p5/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfmops za1.h, p5.h, p5/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid matrix operand + +bfmops za2.h, p5/m, p5/m, z12.h, z11.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfmops za2.h, p5/m, p5/m, z12.h, z11.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid register suffixes + +bfmops za1.h, p5/m, p5/m, z12.h, z11.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfmops za1.h, p5/m, p5/m, z12.h, z11.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfmops.s b/llvm/test/MC/AArch64/SME2/bfmops.s new file mode 100644 index 0000000..2b76986 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfmops.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfmops za0.h, p0/m, p0/m, z0.h, z0.h // 10000001-10100000-00000000-00011000 +// CHECK-INST: bfmops za0.h, p0/m, p0/m, z0.h, z0.h +// CHECK-ENCODING: [0x18,0x00,0xa0,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a00018 <unknown> + +bfmops za1.h, p5/m, p2/m, z10.h, z21.h // 10000001-10110101-01010101-01011001 +// CHECK-INST: bfmops za1.h, p5/m, p2/m, z10.h, z21.h +// CHECK-ENCODING: [0x59,0x55,0xb5,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81b55559 <unknown> + +bfmops za1.h, p3/m, p7/m, z13.h, z8.h // 10000001-10101000-11101101-10111001 +// CHECK-INST: bfmops za1.h, p3/m, p7/m, z13.h, z8.h +// CHECK-ENCODING: [0xb9,0xed,0xa8,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a8edb9 <unknown> + +bfmops za1.h, p7/m, p7/m, z31.h, z31.h // 10000001-10111111-11111111-11111001 +// CHECK-INST: bfmops za1.h, p7/m, p7/m, z31.h, z31.h +// CHECK-ENCODING: [0xf9,0xff,0xbf,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81bffff9 <unknown> + +bfmops za1.h, p3/m, p0/m, z17.h, z16.h // 10000001-10110000-00001110-00111001 +// CHECK-INST: bfmops za1.h, p3/m, p0/m, z17.h, z16.h +// CHECK-ENCODING: [0x39,0x0e,0xb0,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81b00e39 <unknown> + +bfmops za1.h, p1/m, p4/m, z1.h, z30.h // 10000001-10111110-10000100-00111001 +// CHECK-INST: bfmops za1.h, p1/m, p4/m, z1.h, z30.h +// CHECK-ENCODING: [0x39,0x84,0xbe,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81be8439 <unknown> + +bfmops za0.h, p5/m, p2/m, z19.h, z20.h // 10000001-10110100-01010110-01111000 +// CHECK-INST: bfmops za0.h, p5/m, p2/m, z19.h, z20.h +// CHECK-ENCODING: [0x78,0x56,0xb4,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81b45678 <unknown> + +bfmops za0.h, p6/m, p0/m, z12.h, z2.h // 10000001-10100010-00011001-10011000 +// CHECK-INST: bfmops za0.h, p6/m, p0/m, z12.h, z2.h +// CHECK-ENCODING: [0x98,0x19,0xa2,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a21998 <unknown> + +bfmops za1.h, p2/m, p6/m, z1.h, z26.h // 10000001-10111010-11001000-00111001 +// CHECK-INST: bfmops za1.h, p2/m, p6/m, z1.h, z26.h +// CHECK-ENCODING: [0x39,0xc8,0xba,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81bac839 <unknown> + +bfmops za1.h, p2/m, p0/m, z22.h, z30.h // 10000001-10111110-00001010-11011001 +// CHECK-INST: bfmops za1.h, p2/m, p0/m, z22.h, z30.h +// CHECK-ENCODING: [0xd9,0x0a,0xbe,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81be0ad9 <unknown> + +bfmops za0.h, p5/m, p7/m, z9.h, z1.h // 10000001-10100001-11110101-00111000 +// CHECK-INST: bfmops za0.h, p5/m, p7/m, z9.h, z1.h +// CHECK-ENCODING: [0x38,0xf5,0xa1,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81a1f538 <unknown> + +bfmops za1.h, p2/m, p5/m, z12.h, z11.h // 10000001-10101011-10101001-10011001 +// CHECK-INST: bfmops za1.h, p2/m, p5/m, z12.h, z11.h +// CHECK-ENCODING: [0x99,0xa9,0xab,0x81] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: 81aba999 <unknown> diff --git a/llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s new file mode 100644 index 0000000..5dade3e --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s @@ -0,0 +1,53 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Out of range index offset + +bfsub za.h[w8, 8], {z20.h-z21.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfsub za.h[w8, 8], {z20.h-z21.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfsub za.h[w8, -1, vgx4], {z0.h-z3.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. +// CHECK-NEXT: bfsub za.h[w8, -1, vgx4], {z0.h-z3.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector select register + +bfsub za.h[w7, 0], {z20.h-z21.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfsub za.h[w7, 0], {z20.h-z21.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfsub za.h[w12, 0, vgx4], {z20.h-z23.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11] +// CHECK-NEXT: bfsub za.h[w12, 0, vgx4], {z20.h-z23.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector list + +bfsub za.h[w8, 3], {z20.h-z22.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfsub za.h[w8, 3], {z20.h-z22.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfsub za.h[w8, 3, vgx4], {z21.h-z24.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: bfsub za.h[w8, 3, vgx4], {z21.h-z24.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid suffixes + +bfsub za.h[w8, 3, vgx4], {z20.s-z23.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfsub za.h[w8, 3, vgx4], {z20.s-z23.s} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfsub za.d[w8, 3, vgx4], {z20.h-z23.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h +// CHECK-NEXT: bfsub za.d[w8, 3, vgx4], {z20.h-z23.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/bfsub.s b/llvm/test/MC/AArch64/SME2/bfsub.s new file mode 100644 index 0000000..6cfd507 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/bfsub.s @@ -0,0 +1,300 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2,+b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfsub za.h[w8, 0, vgx2], {z0.h, z1.h} // 11000001-11100100-00011100-00001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x08,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c08 <unknown> + +bfsub za.h[w8, 0], {z0.h - z1.h} // 11000001-11100100-00011100-00001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x08,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c08 <unknown> + +bfsub za.h[w10, 5, vgx2], {z10.h, z11.h} // 11000001-11100100-01011101-01001101 +// CHECK-INST: bfsub za.h[w10, 5, vgx2], { z10.h, z11.h } +// CHECK-ENCODING: [0x4d,0x5d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45d4d <unknown> + +bfsub za.h[w10, 5], {z10.h - z11.h} // 11000001-11100100-01011101-01001101 +// CHECK-INST: bfsub za.h[w10, 5, vgx2], { z10.h, z11.h } +// CHECK-ENCODING: [0x4d,0x5d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45d4d <unknown> + +bfsub za.h[w11, 7, vgx2], {z12.h, z13.h} // 11000001-11100100-01111101-10001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x8f,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d8f <unknown> + +bfsub za.h[w11, 7], {z12.h - z13.h} // 11000001-11100100-01111101-10001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x8f,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d8f <unknown> + +bfsub za.h[w11, 7, vgx2], {z30.h, z31.h} // 11000001-11100100-01111111-11001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx2], { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x7f,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47fcf <unknown> + +bfsub za.h[w11, 7], {z30.h - z31.h} // 11000001-11100100-01111111-11001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx2], { z30.h, z31.h } +// CHECK-ENCODING: [0xcf,0x7f,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47fcf <unknown> + +bfsub za.h[w8, 5, vgx2], {z16.h, z17.h} // 11000001-11100100-00011110-00001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx2], { z16.h, z17.h } +// CHECK-ENCODING: [0x0d,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41e0d <unknown> + +bfsub za.h[w8, 5], {z16.h - z17.h} // 11000001-11100100-00011110-00001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx2], { z16.h, z17.h } +// CHECK-ENCODING: [0x0d,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41e0d <unknown> + +bfsub za.h[w8, 1, vgx2], {z0.h, z1.h} // 11000001-11100100-00011100-00001001 +// CHECK-INST: bfsub za.h[w8, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x09,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c09 <unknown> + +bfsub za.h[w8, 1], {z0.h - z1.h} // 11000001-11100100-00011100-00001001 +// CHECK-INST: bfsub za.h[w8, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x09,0x1c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41c09 <unknown> + +bfsub za.h[w10, 0, vgx2], {z18.h, z19.h} // 11000001-11100100-01011110, 01001000 +// CHECK-INST: bfsub za.h[w10, 0, vgx2], { z18.h, z19.h } +// CHECK-ENCODING: [0x48,0x5e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45e48 <unknown> + +bfsub za.h[w10, 0], {z18.h - z19.h} // 11000001-11100100-01011110-01001000 +// CHECK-INST: bfsub za.h[w10, 0, vgx2], { z18.h, z19.h } +// CHECK-ENCODING: [0x48,0x5e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45e48 <unknown> + +bfsub za.h[w8, 0, vgx2], {z12.h, z13.h} // 11000001-11100100-00011101-10001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x88,0x1d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41d88 <unknown> + +bfsub za.h[w8, 0], {z12.h - z13.h} // 11000001-11100100-00011101-10001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x88,0x1d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41d88 <unknown> + +bfsub za.h[w10, 1, vgx2], {z0.h, z1.h} // 11000001-11100100-01011100-00001001 +// CHECK-INST: bfsub za.h[w10, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x09,0x5c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45c09 <unknown> + +bfsub za.h[w10, 1], {z0.h - z1.h} // 11000001-11100100-01011100-00001001 +// CHECK-INST: bfsub za.h[w10, 1, vgx2], { z0.h, z1.h } +// CHECK-ENCODING: [0x09,0x5c,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e45c09 <unknown> + +bfsub za.h[w8, 5, vgx2], {z22.h, z23.h} // 11000001-11100100-00011110, 11001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx2], { z22.h, z23.h } +// CHECK-ENCODING: [0xcd,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41ecd <unknown> + +bfsub za.h[w8, 5], {z22.h - z23.h} // 11000001-11100100-00011110-11001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx2], { z22.h, z23.h } +// CHECK-ENCODING: [0xcd,0x1e,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e41ecd <unknown> + +bfsub za.h[w11, 2, vgx2], {z8.h, z9.h} // 11000001-11100100-01111101-00001010 +// CHECK-INST: bfsub za.h[w11, 2, vgx2], { z8.h, z9.h } +// CHECK-ENCODING: [0x0a,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d0a <unknown> + +bfsub za.h[w11, 2], {z8.h - z9.h} // 11000001-11100100-01111101-00001010 +// CHECK-INST: bfsub za.h[w11, 2, vgx2], { z8.h, z9.h } +// CHECK-ENCODING: [0x0a,0x7d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e47d0a <unknown> + +bfsub za.h[w9, 7, vgx2], {z12.h, z13.h} // 11000001-11100100-00111101-10001111 +// CHECK-INST: bfsub za.h[w9, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x8f,0x3d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e43d8f <unknown> + +bfsub za.h[w9, 7], {z12.h - z13.h} // 11000001-11100100-00111101-10001111 +// CHECK-INST: bfsub za.h[w9, 7, vgx2], { z12.h, z13.h } +// CHECK-ENCODING: [0x8f,0x3d,0xe4,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e43d8f <unknown> + +bfsub za.h[w8, 0, vgx4], {z0.h - z3.h} // 11000001-11100101-00011100-00001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x08,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c08 <unknown> + +bfsub za.h[w8, 0], {z0.h - z3.h} // 11000001-11100101-00011100-00001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x08,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c08 <unknown> + +bfsub za.h[w10, 5, vgx4], {z8.h - z11.h} // 11000001-11100101-01011101-00001101 +// CHECK-INST: bfsub za.h[w10, 5, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x0d,0x5d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55d0d <unknown> + +bfsub za.h[w10, 5], {z8.h - z11.h} // 11000001-11100101-01011101-00001101 +// CHECK-INST: bfsub za.h[w10, 5, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x0d,0x5d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55d0d <unknown> + +bfsub za.h[w11, 7, vgx4], {z12.h - z15.h} // 11000001-11100101-01111101-10001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x8f,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d8f <unknown> + +bfsub za.h[w11, 7], {z12.h - z15.h} // 11000001-11100101-01111101-10001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x8f,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d8f <unknown> + +bfsub za.h[w11, 7, vgx4], {z28.h - z31.h} // 11000001-11100101-01111111-10001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx4], { z28.h - z31.h } +// CHECK-ENCODING: [0x8f,0x7f,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57f8f <unknown> + +bfsub za.h[w11, 7], {z28.h - z31.h} // 11000001-11100101-01111111-10001111 +// CHECK-INST: bfsub za.h[w11, 7, vgx4], { z28.h - z31.h } +// CHECK-ENCODING: [0x8f,0x7f,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57f8f <unknown> + +bfsub za.h[w8, 5, vgx4], {z16.h - z19.h} // 11000001-11100101-00011110-00001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x0d,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e0d <unknown> + +bfsub za.h[w8, 5], {z16.h - z19.h} // 11000001-11100101-00011110-00001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x0d,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e0d <unknown> + +bfsub za.h[w8, 1, vgx4], {z0.h - z3.h} // 11000001-11100101-00011100-00001001 +// CHECK-INST: bfsub za.h[w8, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x09,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c09 <unknown> + +bfsub za.h[w8, 1], {z0.h - z3.h} // 11000001-11100101-00011100-00001001 +// CHECK-INST: bfsub za.h[w8, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x09,0x1c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51c09 <unknown> + +bfsub za.h[w10, 0, vgx4], {z16.h - z19.h} // 11000001-11100101-01011110-00001000 +// CHECK-INST: bfsub za.h[w10, 0, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x08,0x5e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55e08 <unknown> + +bfsub za.h[w10, 0], {z16.h - z19.h} // 11000001-11100101-01011110-00001000 +// CHECK-INST: bfsub za.h[w10, 0, vgx4], { z16.h - z19.h } +// CHECK-ENCODING: [0x08,0x5e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55e08 <unknown> + +bfsub za.h[w8, 0, vgx4], {z12.h - z15.h} // 11000001-11100101-00011101-10001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x88,0x1d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51d88 <unknown> + +bfsub za.h[w8, 0], {z12.h - z15.h} // 11000001-11100101-00011101-10001000 +// CHECK-INST: bfsub za.h[w8, 0, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x88,0x1d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51d88 <unknown> + +bfsub za.h[w10, 1, vgx4], {z0.h - z3.h} // 11000001-11100101-01011100-00001001 +// CHECK-INST: bfsub za.h[w10, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x09,0x5c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55c09 <unknown> + +bfsub za.h[w10, 1], {z0.h - z3.h} // 11000001-11100101-01011100-00001001 +// CHECK-INST: bfsub za.h[w10, 1, vgx4], { z0.h - z3.h } +// CHECK-ENCODING: [0x09,0x5c,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e55c09 <unknown> + +bfsub za.h[w8, 5, vgx4], {z20.h - z23.h} // 11000001-11100101-00011110-10001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx4], { z20.h - z23.h } +// CHECK-ENCODING: [0x8d,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e8d <unknown> + +bfsub za.h[w8, 5], {z20.h - z23.h} // 11000001-11100101-00011110-10001101 +// CHECK-INST: bfsub za.h[w8, 5, vgx4], { z20.h - z23.h } +// CHECK-ENCODING: [0x8d,0x1e,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e51e8d <unknown> + +bfsub za.h[w11, 2, vgx4], {z8.h - z11.h} // 11000001-11100101-01111101-00001010 +// CHECK-INST: bfsub za.h[w11, 2, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x0a,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d0a <unknown> + +bfsub za.h[w11, 2], {z8.h - z11.h} // 11000001-11100101-01111101-00001010 +// CHECK-INST: bfsub za.h[w11, 2, vgx4], { z8.h - z11.h } +// CHECK-ENCODING: [0x0a,0x7d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e57d0a <unknown> + +bfsub za.h[w9, 7, vgx4], {z12.h - z15.h} // 11000001-11100101-00111101-10001111 +// CHECK-INST: bfsub za.h[w9, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x8f,0x3d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e53d8f <unknown> + +bfsub za.h[w9, 7], {z12.h - z15.h} // 11000001-11100101-00111101-10001111 +// CHECK-INST: bfsub za.h[w9, 7, vgx4], { z12.h - z15.h } +// CHECK-ENCODING: [0x8f,0x3d,0xe5,0xc1] +// CHECK-ERROR: instruction requires: b16b16 sme2 +// CHECK-UNKNOWN: c1e53d8f <unknown> |