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-rw-r--r--llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s53
1 files changed, 53 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s b/llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s
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index 0000000..5dade3e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/bfsub-diagnostics.s
@@ -0,0 +1,53 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+b16b16 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Out of range index offset
+
+bfsub za.h[w8, 8], {z20.h-z21.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: bfsub za.h[w8, 8], {z20.h-z21.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfsub za.h[w8, -1, vgx4], {z0.h-z3.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK-NEXT: bfsub za.h[w8, -1, vgx4], {z0.h-z3.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector select register
+
+bfsub za.h[w7, 0], {z20.h-z21.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfsub za.h[w7, 0], {z20.h-z21.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfsub za.h[w12, 0, vgx4], {z20.h-z23.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
+// CHECK-NEXT: bfsub za.h[w12, 0, vgx4], {z20.h-z23.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+bfsub za.h[w8, 3], {z20.h-z22.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfsub za.h[w8, 3], {z20.h-z22.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfsub za.h[w8, 3, vgx4], {z21.h-z24.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: bfsub za.h[w8, 3, vgx4], {z21.h-z24.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid suffixes
+
+bfsub za.h[w8, 3, vgx4], {z20.s-z23.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfsub za.h[w8, 3, vgx4], {z20.s-z23.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfsub za.d[w8, 3, vgx4], {z20.h-z23.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
+// CHECK-NEXT: bfsub za.d[w8, 3, vgx4], {z20.h-z23.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: