diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
22 files changed, 14171 insertions, 274 deletions
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir new file mode 100644 index 0000000..eda1180 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir @@ -0,0 +1,902 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir \ +# RUN: -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: anyext_nxv1i16_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s16>) = G_ANYEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i32_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s32>) = G_ANYEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_ANYEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i16_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s16>) = G_ANYEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s32>) = G_ANYEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_ANYEXT %0(<vscale x 2 x s8>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i16_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s16>) = G_ANYEXT %0(<vscale x 4 x s8>) + $v8 = COPY %1(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv4i32_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s32>) = G_ANYEXT %0(<vscale x 4 x s8>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s64>) = G_ANYEXT %0(<vscale x 4 x s8>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i16_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s16>) = G_ANYEXT %0(<vscale x 8 x s8>) + $v8m2 = COPY %1(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv8i32_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s32>) = G_ANYEXT %0(<vscale x 8 x s8>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s64>) = G_ANYEXT %0(<vscale x 8 x s8>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i16_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 16 x s8>) = COPY $v8m2 + %1:vrb(<vscale x 16 x s16>) = G_ANYEXT %0(<vscale x 16 x s8>) + $v8m4 = COPY %1(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv16i32_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 16 x s8>) = COPY $v8m4 + %1:vrb(<vscale x 16 x s32>) = G_ANYEXT %0(<vscale x 16 x s8>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv32i16_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 32 x s8>) = COPY $v8m4 + %1:vrb(<vscale x 32 x s16>) = G_ANYEXT %0(<vscale x 32 x s8>) + $v8m8 = COPY %1(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i32_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = COPY $v8 + %1:vrb(<vscale x 1 x s32>) = G_ANYEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_ANYEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s16>) = COPY $v8 + %1:vrb(<vscale x 2 x s32>) = G_ANYEXT %0(<vscale x 2 x s16>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s16>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_ANYEXT %0(<vscale x 2 x s16>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i32_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 4 x s16>) = COPY $v8 + %1:vrb(<vscale x 4 x s32>) = G_ANYEXT %0(<vscale x 4 x s16>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s16>) = COPY $v8 + %1:vrb(<vscale x 4 x s64>) = G_ANYEXT %0(<vscale x 4 x s16>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i32_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 8 x s16>) = COPY $v8m2 + %1:vrb(<vscale x 8 x s32>) = G_ANYEXT %0(<vscale x 8 x s16>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s16>) = COPY $v8m2 + %1:vrb(<vscale x 8 x s64>) = G_ANYEXT %0(<vscale x 8 x s16>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i32_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 16 x s16>) = COPY $v8m4 + %1:vrb(<vscale x 16 x s32>) = G_ANYEXT %0(<vscale x 16 x s16>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i64_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s32>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_ANYEXT %0(<vscale x 1 x s32>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s32>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_ANYEXT %0(<vscale x 2 x s32>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s32>) = COPY $v8m2 + %1:vrb(<vscale x 4 x s64>) = G_ANYEXT %0(<vscale x 4 x s32>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s32>) = COPY $v8m4 + %1:vrb(<vscale x 8 x s64>) = G_ANYEXT %0(<vscale x 8 x s32>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir new file mode 100644 index 0000000..df0d48a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir @@ -0,0 +1,534 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +# Don't test i1 element types here since they have been widened to i8 in legalization + +--- +name: icmp_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(ult), %0(<vscale x 1 x s8>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(slt), %0(<vscale x 2 x s8>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(uge), %0(<vscale x 4 x s8>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i8 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i8 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sge), %0(<vscale x 8 x s8>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i8 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i8 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 16 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(ugt), %0(<vscale x 16 x s8>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i8 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i8 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 32 x s8>), %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv64i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv64i8 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv64i8 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 64 x s8>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 64 x s1>) = G_ICMP intpred(ule), %0(<vscale x 64 x s8>), %0 + $v8 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i16 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i16 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sle), %0(<vscale x 1 x s16>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i16 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i16 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s16>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ne), %0(<vscale x 2 x s16>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i16 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i16 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(eq), %0(<vscale x 4 x s16>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i16 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i16 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 8 x s16>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ult), %0(<vscale x 8 x s16>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i16 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i16 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(slt), %0(<vscale x 16 x s16>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i16 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i16 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 32 x s16>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 32 x s1>) = G_ICMP intpred(uge), %0(<vscale x 32 x s16>), %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i32 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i32 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sge), %0(<vscale x 1 x s32>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i32 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i32 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s32>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ugt), %0(<vscale x 2 x s32>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i32 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i32 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s32>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i32 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i32 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 8 x s32>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ule), %0(<vscale x 8 x s32>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i32 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i32 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sle), %0(<vscale x 16 x s32>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i64 + ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i64 + ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s64>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(eq), %0(<vscale x 1 x s64>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i64 + ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i64 + ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ne), %0(<vscale x 2 x s64>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i64 + ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i64 + ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s64>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(ult), %0(<vscale x 4 x s64>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i64 + ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i64 + ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF + %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ult), %0(<vscale x 8 x s64>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir new file mode 100644 index 0000000..382166f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir @@ -0,0 +1,900 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: sext_nxv1i16_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s16>) = G_SEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i32_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s32>) = G_SEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_SEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i16_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s16>) = G_SEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s32>) = G_SEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_SEXT %0(<vscale x 2 x s8>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i16_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s16>) = G_SEXT %0(<vscale x 4 x s8>) + $v8 = COPY %1(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv4i32_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s32>) = G_SEXT %0(<vscale x 4 x s8>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s64>) = G_SEXT %0(<vscale x 4 x s8>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i16_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s16>) = G_SEXT %0(<vscale x 8 x s8>) + $v8m2 = COPY %1(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv8i32_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s32>) = G_SEXT %0(<vscale x 8 x s8>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s64>) = G_SEXT %0(<vscale x 8 x s8>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i16_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 16 x s8>) = COPY $v8m2 + %1:vrb(<vscale x 16 x s16>) = G_SEXT %0(<vscale x 16 x s8>) + $v8m4 = COPY %1(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv16i32_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 16 x s8>) = COPY $v8m2 + %1:vrb(<vscale x 16 x s32>) = G_SEXT %0(<vscale x 16 x s8>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv32i16_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 32 x s8>) = COPY $v8m4 + %1:vrb(<vscale x 32 x s16>) = G_SEXT %0(<vscale x 32 x s8>) + $v8m8 = COPY %1(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i32_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = COPY $v8 + %1:vrb(<vscale x 1 x s32>) = G_SEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_SEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s16>) = COPY $v8 + %1:vrb(<vscale x 2 x s32>) = G_SEXT %0(<vscale x 2 x s16>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s16>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_SEXT %0(<vscale x 2 x s16>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i32_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 4 x s16>) = COPY $v8 + %1:vrb(<vscale x 4 x s32>) = G_SEXT %0(<vscale x 4 x s16>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s16>) = COPY $v8 + %1:vrb(<vscale x 4 x s64>) = G_SEXT %0(<vscale x 4 x s16>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i32_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 8 x s16>) = COPY $v8m2 + %1:vrb(<vscale x 8 x s32>) = G_SEXT %0(<vscale x 8 x s16>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s16>) = COPY $v8m2 + %1:vrb(<vscale x 8 x s64>) = G_SEXT %0(<vscale x 8 x s16>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i32_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 16 x s16>) = COPY $v8m4 + %1:vrb(<vscale x 16 x s32>) = G_SEXT %0(<vscale x 16 x s16>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i64_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s32>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_SEXT %0(<vscale x 1 x s32>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s32>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_SEXT %0(<vscale x 2 x s32>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s32>) = COPY $v8m2 + %1:vrb(<vscale x 4 x s64>) = G_SEXT %0(<vscale x 4 x s32>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s32>) = COPY $v8m4 + %1:vrb(<vscale x 8 x s64>) = G_SEXT %0(<vscale x 8 x s32>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir new file mode 100644 index 0000000..2fc9e05 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir @@ -0,0 +1,900 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s + +--- +name: zext_nxv1i16_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s16>) = G_ZEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i32_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s8>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i16_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s16>) = G_ZEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s8>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s8>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i16_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s16>) = G_ZEXT %0(<vscale x 4 x s8>) + $v8 = COPY %1(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv4i32_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s8>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s8>) = COPY $v8 + %1:vrb(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s8>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i16_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s16>) = G_ZEXT %0(<vscale x 8 x s8>) + $v8m2 = COPY %1(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv8i32_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s8>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s8>) = COPY $v8 + %1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s8>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i16_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 16 x s8>) = COPY $v8m2 + %1:vrb(<vscale x 16 x s16>) = G_ZEXT %0(<vscale x 16 x s8>) + $v8m4 = COPY %1(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv16i32_nxv16i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 16 x s8>) = COPY $v8m2 + %1:vrb(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s8>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv32i16_nxv32i8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 32 x s8>) = COPY $v8m4 + %1:vrb(<vscale x 32 x s16>) = G_ZEXT %0(<vscale x 32 x s8>) + $v8m8 = COPY %1(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i32_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = COPY $v8 + %1:vrb(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s16>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 2 x s16>) = COPY $v8 + %1:vrb(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s16>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s16>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s16>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i32_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 4 x s16>) = COPY $v8 + %1:vrb(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s16>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s16>) = COPY $v8 + %1:vrb(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s16>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i32_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 8 x s16>) = COPY $v8m2 + %1:vrb(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s16>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s16>) = COPY $v8m4 + %1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s16>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i32_nxv16i16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 16 x s16>) = COPY $v8m4 + %1:vrb(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s16>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i64_nxv1i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:vrb(<vscale x 1 x s32>) = COPY $v8 + %1:vrb(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s32>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m2 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m2 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:vrb(<vscale x 2 x s32>) = COPY $v8 + %1:vrb(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s32>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m4 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m4 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:vrb(<vscale x 4 x s32>) = COPY $v8m2 + %1:vrb(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s32>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: $v8m8 = COPY %1 + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 + ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: $v8m8 = COPY %1 + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:vrb(<vscale x 8 x s32>) = COPY $v8m4 + %1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s32>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir new file mode 100644 index 0000000..3a2d40f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir @@ -0,0 +1,1589 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +# Extend from s1 element vectors +--- +name: anyext_nxv1i8_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i8_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i8_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s8>) = G_ANYEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s8>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i16_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i16_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i16_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s16>) = G_ANYEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s16>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i32_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i32_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i32_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s32>) = G_ANYEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i64_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s64>) = G_ANYEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i8_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i8_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i8_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s8>) = G_ANYEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s8>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i16_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i16_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i16_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s16>) = G_ANYEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s16>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i32_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i32_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i32_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s32>) = G_ANYEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s64>) = G_ANYEXT %1(<vscale x 2 x s1>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i8_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i8_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv4i8_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s8>) = G_ANYEXT %1(<vscale x 4 x s1>) + $v8 = COPY %0(<vscale x 4 x s8>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv4i16_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i16_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv4i16_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s16>) = G_ANYEXT %1(<vscale x 4 x s1>) + $v8 = COPY %0(<vscale x 4 x s16>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv4i32_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i32_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv4i32_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s32>) = G_ANYEXT %1(<vscale x 4 x s1>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s64>) = G_ANYEXT %1(<vscale x 4 x s1>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i8_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i8_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 8 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv8i8_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 8 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s8>) = G_ANYEXT %1(<vscale x 8 x s1>) + $v8 = COPY %0(<vscale x 8 x s8>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv8i16_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i16_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 8 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv8i16_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 8 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s16>) = G_ANYEXT %1(<vscale x 8 x s1>) + $v8m2 = COPY %0(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv8i32_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i32_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv8i32_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s32>) = G_ANYEXT %1(<vscale x 8 x s1>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s64>) = G_ANYEXT %1(<vscale x 8 x s1>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv16i8_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv16i8_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 16 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv16i8_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 16 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 16 x s1>) = COPY $v0 + %0:_(<vscale x 16 x s8>) = G_ANYEXT %1(<vscale x 16 x s1>) + $v8m2 = COPY %0(<vscale x 16 x s8>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv16i16_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv16i16_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 16 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv16i16_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 16 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 16 x s1>) = COPY $v0 + %0:_(<vscale x 16 x s16>) = G_ANYEXT %1(<vscale x 16 x s1>) + $v8m4 = COPY %0(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv16i32_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv16i32_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv16i32_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s1>) = COPY $v0 + %0:_(<vscale x 16 x s32>) = G_ANYEXT %1(<vscale x 16 x s1>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv32i8_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv32i8_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 32 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv32i8_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 32 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 32 x s1>) = COPY $v0 + %0:_(<vscale x 32 x s8>) = G_ANYEXT %1(<vscale x 32 x s1>) + $v8m4 = COPY %0(<vscale x 32 x s8>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv32i16_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv32i16_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 32 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv32i16_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 32 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 32 x s1>) = COPY $v0 + %0:_(<vscale x 32 x s16>) = G_ANYEXT %1(<vscale x 32 x s1>) + $v8m8 = COPY %0(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv64i8_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: anyext_nxv64i8_nxv64i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[COPY]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 64 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv64i8_nxv64i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[COPY]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 64 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 64 x s1>) = COPY $v0 + %0:_(<vscale x 64 x s8>) = G_ANYEXT %1(<vscale x 64 x s1>) + $v8m8 = COPY %0(<vscale x 64 x s8>) + PseudoRET implicit $v8m8 +... + +# Extend from s8 element vectors +--- +name: anyext_nxv1i16_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s16>) = G_ANYEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s16>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i32_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_ANYEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i64_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ANYEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i16_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s16>) = G_ANYEXT %1(<vscale x 2 x s8>) + $v8 = COPY %0(<vscale x 2 x s16>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i32_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_ANYEXT %1(<vscale x 2 x s8>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ANYEXT %1(<vscale x 2 x s8>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i16_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 4 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 4 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s16>) = G_ANYEXT %1(<vscale x 4 x s8>) + $v8 = COPY %0(<vscale x 4 x s16>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv4i32_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_ANYEXT %1(<vscale x 4 x s8>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_ANYEXT %1(<vscale x 4 x s8>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i16_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 8 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 8 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s16>) = G_ANYEXT %1(<vscale x 8 x s8>) + $v8m2 = COPY %0(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv8i32_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s32>) = G_ANYEXT %1(<vscale x 8 x s8>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s64>) = G_ANYEXT %1(<vscale x 8 x s8>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv16i16_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 16 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 16 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 16 x s8>) = COPY $v8m2 + %0:_(<vscale x 16 x s16>) = G_ANYEXT %1(<vscale x 16 x s8>) + $v8m4 = COPY %0(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv16i32_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s8>) = COPY $v8m4 + %0:_(<vscale x 16 x s32>) = G_ANYEXT %1(<vscale x 16 x s8>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv32i16_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_ANYEXT [[COPY]](<vscale x 32 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 32 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_ANYEXT [[COPY]](<vscale x 32 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 32 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 32 x s8>) = COPY $v8m4 + %0:_(<vscale x 32 x s16>) = G_ANYEXT %1(<vscale x 32 x s8>) + $v8m8 = COPY %0(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 +... + +# Extend from s16 element vectors +--- +name: anyext_nxv1i32_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s16>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_ANYEXT %1(<vscale x 1 x s16>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv1i64_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s16>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ANYEXT %1(<vscale x 1 x s16>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i32_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s16>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_ANYEXT %1(<vscale x 2 x s16>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s16>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ANYEXT %1(<vscale x 2 x s16>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i32_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s16>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_ANYEXT %1(<vscale x 4 x s16>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s16>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_ANYEXT %1(<vscale x 4 x s16>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i32_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s16>) = COPY $v8m2 + %0:_(<vscale x 8 x s32>) = G_ANYEXT %1(<vscale x 8 x s16>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s16>) = COPY $v8m2 + %0:_(<vscale x 8 x s64>) = G_ANYEXT %1(<vscale x 8 x s16>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: anyext_nxv16i32_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s16>) + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s16>) + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s16>) = COPY $v8m4 + %0:_(<vscale x 16 x s32>) = G_ANYEXT %1(<vscale x 16 x s16>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... + +# Extend from s32 element vectors +--- +name: anyext_nxv1i64_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s32>) + ; RV32-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s32>) + ; RV64-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s32>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ANYEXT %1(<vscale x 1 x s32>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: anyext_nxv2i64_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s32>) + ; RV32-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s32>) + ; RV64-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s32>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ANYEXT %1(<vscale x 2 x s32>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: anyext_nxv4i64_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s32>) + ; RV32-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s32>) + ; RV64-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s32>) = COPY $v8m2 + %0:_(<vscale x 4 x s64>) = G_ANYEXT %1(<vscale x 4 x s32>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: anyext_nxv8i64_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 + ; RV32-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s32>) + ; RV32-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s32>) + ; RV64-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s32>) = COPY $v8m4 + %0:_(<vscale x 8 x s64>) = G_ANYEXT %1(<vscale x 8 x s32>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir new file mode 100644 index 0000000..d1df954 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir @@ -0,0 +1,810 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +--- +name: icmp_nxv1i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 1 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[DEF]](<vscale x 1 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 1 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 2 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 2 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 4 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 4 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 8 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 8 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 16 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[DEF]](<vscale x 16 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 16 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv32i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv32i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 32 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv32i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[DEF]](<vscale x 32 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 32 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv64i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv64i1 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C3]](s32) + ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 64 x s8>), [[SELECT1]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv64i1 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT2]](s64) + ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT3]](s64) + ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]] + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[SELECT]](<vscale x 64 x s8>), [[SELECT1]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv32i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv32i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv64i8 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s8>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv64i8 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s8>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i16 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s16>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i16 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s16>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i16 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s16>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i16 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s16>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i16 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s16>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i16 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s16>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i16 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s16>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i16 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s16>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i16 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s16>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i16 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s16>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv32i16 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s16>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv32i16 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s16>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i32 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s32>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i32 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s32>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i32 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s32>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i32 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s32>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i32 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s32>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i32 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s32>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i32 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s32>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i32 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s32>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv16i32 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s32>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv16i32 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s32>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv1i64 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s64>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv1i64 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s64>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv2i64 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s64>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv2i64 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s64>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv4i64 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s64>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv4i64 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s64>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 +... +--- +name: icmp_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32-LABEL: name: icmp_nxv8i64 + ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF + ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s64>), [[DEF]] + ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: icmp_nxv8i64 + ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF + ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s64>), [[DEF]] + ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0, %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir new file mode 100644 index 0000000..1571daf --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir @@ -0,0 +1,1589 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +# Extend from s1 element vectors +--- +name: sext_nxv1i8_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i8_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i8_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s8>) = G_SEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s8>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i16_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i16_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i16_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s16>) = G_SEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s16>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i32_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i32_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i32_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s32>) = G_SEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i64_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v0 + %0:_(<vscale x 1 x s64>) = G_SEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i8_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i8_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i8_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s8>) = G_SEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s8>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i16_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i16_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i16_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s16>) = G_SEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s16>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i32_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i32_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i32_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s32>) = G_SEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s1>) = COPY $v0 + %0:_(<vscale x 2 x s64>) = G_SEXT %1(<vscale x 2 x s1>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i8_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i8_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv4i8_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s8>) = G_SEXT %1(<vscale x 4 x s1>) + $v8 = COPY %0(<vscale x 4 x s8>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv4i16_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i16_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv4i16_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s16>) = G_SEXT %1(<vscale x 4 x s1>) + $v8 = COPY %0(<vscale x 4 x s16>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv4i32_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i32_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv4i32_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s32>) = G_SEXT %1(<vscale x 4 x s1>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s1>) = COPY $v0 + %0:_(<vscale x 4 x s64>) = G_SEXT %1(<vscale x 4 x s1>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i8_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i8_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 8 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv8i8_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 8 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s8>) = G_SEXT %1(<vscale x 8 x s1>) + $v8 = COPY %0(<vscale x 8 x s8>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv8i16_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i16_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 8 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv8i16_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 8 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s16>) = G_SEXT %1(<vscale x 8 x s1>) + $v8m2 = COPY %0(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv8i32_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i32_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv8i32_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s32>) = G_SEXT %1(<vscale x 8 x s1>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s1>) = COPY $v0 + %0:_(<vscale x 8 x s64>) = G_SEXT %1(<vscale x 8 x s1>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv16i8_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv16i8_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 16 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv16i8_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 16 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 16 x s1>) = COPY $v0 + %0:_(<vscale x 16 x s8>) = G_SEXT %1(<vscale x 16 x s1>) + $v8m2 = COPY %0(<vscale x 16 x s8>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv16i16_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv16i16_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 16 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv16i16_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 16 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 16 x s1>) = COPY $v0 + %0:_(<vscale x 16 x s16>) = G_SEXT %1(<vscale x 16 x s1>) + $v8m4 = COPY %0(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv16i32_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv16i32_nxv16i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv16i32_nxv16i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s1>) = COPY $v0 + %0:_(<vscale x 16 x s32>) = G_SEXT %1(<vscale x 16 x s1>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv32i8_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv32i8_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 32 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv32i8_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 32 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 32 x s1>) = COPY $v0 + %0:_(<vscale x 32 x s8>) = G_SEXT %1(<vscale x 32 x s1>) + $v8m4 = COPY %0(<vscale x 32 x s8>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv32i16_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv32i16_nxv32i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 32 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv32i16_nxv32i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 32 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 32 x s1>) = COPY $v0 + %0:_(<vscale x 32 x s16>) = G_SEXT %1(<vscale x 32 x s1>) + $v8m8 = COPY %0(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv64i8_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v0 + ; RV32-LABEL: name: sext_nxv64i8_nxv64i1 + ; RV32: liveins: $v0 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[COPY]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 64 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv64i8_nxv64i1 + ; RV64: liveins: $v0 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[COPY]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 64 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 64 x s1>) = COPY $v0 + %0:_(<vscale x 64 x s8>) = G_SEXT %1(<vscale x 64 x s1>) + $v8m8 = COPY %0(<vscale x 64 x s8>) + PseudoRET implicit $v8m8 +... + +# Extend from s8 element vectors +--- +name: sext_nxv1i16_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s16>) = G_SEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s16>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i32_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_SEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i64_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_SEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i16_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s16>) = G_SEXT %1(<vscale x 2 x s8>) + $v8 = COPY %0(<vscale x 2 x s16>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i32_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_SEXT %1(<vscale x 2 x s8>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_SEXT %1(<vscale x 2 x s8>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i16_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 4 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 4 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s16>) = G_SEXT %1(<vscale x 4 x s8>) + $v8 = COPY %0(<vscale x 4 x s16>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv4i32_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_SEXT %1(<vscale x 4 x s8>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_SEXT %1(<vscale x 4 x s8>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i16_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 8 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 8 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s16>) = G_SEXT %1(<vscale x 8 x s8>) + $v8m2 = COPY %0(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv8i32_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s32>) = G_SEXT %1(<vscale x 8 x s8>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s64>) = G_SEXT %1(<vscale x 8 x s8>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv16i16_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 16 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 16 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 16 x s8>) = COPY $v8m2 + %0:_(<vscale x 16 x s16>) = G_SEXT %1(<vscale x 16 x s8>) + $v8m4 = COPY %0(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv16i32_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s8>) = COPY $v8m2 + %0:_(<vscale x 16 x s32>) = G_SEXT %1(<vscale x 16 x s8>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv32i16_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SEXT [[COPY]](<vscale x 32 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 32 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SEXT [[COPY]](<vscale x 32 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 32 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 32 x s8>) = COPY $v8m4 + %0:_(<vscale x 32 x s16>) = G_SEXT %1(<vscale x 32 x s8>) + $v8m8 = COPY %0(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 +... + +# Extend from s16 element vectors +--- +name: sext_nxv1i32_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s16>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_SEXT %1(<vscale x 1 x s16>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv1i64_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s16>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_SEXT %1(<vscale x 1 x s16>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i32_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s16>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_SEXT %1(<vscale x 2 x s16>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV32-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV64-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s16>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_SEXT %1(<vscale x 2 x s16>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i32_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV32-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV64-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s16>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_SEXT %1(<vscale x 4 x s16>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV32-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV64-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s16>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_SEXT %1(<vscale x 4 x s16>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i32_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV32-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV64-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s16>) = COPY $v8m2 + %0:_(<vscale x 8 x s32>) = G_SEXT %1(<vscale x 8 x s16>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV32-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV64-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s16>) = COPY $v8m2 + %0:_(<vscale x 8 x s64>) = G_SEXT %1(<vscale x 8 x s16>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: sext_nxv16i32_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s16>) + ; RV32-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s16>) + ; RV64-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s16>) = COPY $v8m4 + %0:_(<vscale x 16 x s32>) = G_SEXT %1(<vscale x 16 x s16>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... + +# Extend from s32 element vectors +--- +name: sext_nxv1i64_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s32>) + ; RV32-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s32>) + ; RV64-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s32>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_SEXT %1(<vscale x 1 x s32>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: sext_nxv2i64_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s32>) + ; RV32-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s32>) + ; RV64-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s32>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_SEXT %1(<vscale x 2 x s32>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: sext_nxv4i64_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s32>) + ; RV32-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s32>) + ; RV64-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s32>) = COPY $v8m2 + %0:_(<vscale x 4 x s64>) = G_SEXT %1(<vscale x 4 x s32>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: sext_nxv8i64_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 + ; RV32-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s32>) + ; RV32-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 + ; RV64-NEXT: [[SEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s32>) + ; RV64-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s32>) = COPY $v8m4 + %0:_(<vscale x 8 x s64>) = G_SEXT %1(<vscale x 8 x s32>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir new file mode 100644 index 0000000..109536a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir @@ -0,0 +1,694 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: splatvector_nxv1i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv1i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 1 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 1 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 1 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv2i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv2i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 2 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 2 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv4i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv4i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 4 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 4 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 4 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv8i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv8i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 8 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 8 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 8 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv16i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv16i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 16 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 16 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 16 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv32i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv32i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 32 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 32 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 32 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv64i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 64 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv64i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[AND1]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C2]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 64 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 64 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s32) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s32) + %2:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 64 x s1>) + PseudoRET implicit $v0 +... + +--- +name: splatvector_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 1 x s8>) + PseudoRET implicit $v8 + +... + +--- +name: splatvector_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 2 x s8>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 4 x s8>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 8 x s8>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8m2 = COPY %2(<vscale x 16 x s8>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8m2 = COPY %2(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8m4 = COPY %2(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8m2 = COPY %2(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8m4 = COPY %2(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv16i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8m8 = COPY %2(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir new file mode 100644 index 0000000..7bf5f83 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir @@ -0,0 +1,817 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: splatvector_nxv1i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv1i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv1i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 1 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 1 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 1 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 1 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv2i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv2i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv2i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 2 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 2 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv4i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv4i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv4i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 4 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 4 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 4 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv8i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv8i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv8i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 8 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 8 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 8 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv16i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv16i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv16i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 16 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 16 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 16 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 16 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv32i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv32i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv32i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv32i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 32 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 32 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 32 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 32 x s1>) + PseudoRET implicit $v0 +... +--- +name: splatvector_nxv64i1_0 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_0 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 0 + %1:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_1 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv64i1_1 + ; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0 + ; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 64 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s1) = G_CONSTANT i1 1 + %1:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %0(s1) + $v0 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v0 + +... +--- +name: splatvector_nxv64i1_2 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x10 + + ; CHECK-LABEL: name: splatvector_nxv64i1_2 + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND1]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 64 x s1>) = G_ICMP intpred(ne), [[SPLAT_VECTOR]](<vscale x 64 x s8>), [[SPLAT_VECTOR1]] + ; CHECK-NEXT: $v0 = COPY [[ICMP]](<vscale x 64 x s1>) + ; CHECK-NEXT: PseudoRET implicit $v0 + %0:_(s64) = COPY $x10 + %1:_(s1) = G_TRUNC %0(s64) + %2:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR %1(s1) + $v0 = COPY %2(<vscale x 64 x s1>) + PseudoRET implicit $v0 +... + +--- +name: splatvector_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 1 x s8>) + PseudoRET implicit $v8 + +... + +--- +name: splatvector_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 2 x s8>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 4 x s8>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8 = COPY %2(<vscale x 8 x s8>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i8 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF + %1:_(s8) = G_CONSTANT i8 0 + %2:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %1(s8) + $v8m2 = COPY %2(<vscale x 16 x s8>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8 = COPY %2(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8m2 = COPY %2(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i16 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>) + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF + %1:_(s16) = G_CONSTANT i16 0 + %2:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR %1(s16) + $v8m4 = COPY %2(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8 = COPY %2(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8m2 = COPY %2(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8m4 = COPY %2(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv16i32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv16i32 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>) + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF + %1:_(s32) = G_CONSTANT i32 0 + %2:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR %1(s32) + $v8m8 = COPY %2(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: splatvector_nxv1i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv1i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>) + ; CHECK-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR %1(s64) + $v8 = COPY %2(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv2i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>) + ; CHECK-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %1(s64) + $v8m2 = COPY %2(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv4i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>) + ; CHECK-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR %1(s64) + $v8m4 = COPY %2(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: splatvector_nxv8i64 + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>) + ; CHECK-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF + %1:_(s64) = G_CONSTANT i64 0 + %2:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR %1(s64) + $v8m8 = COPY %2(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir new file mode 100644 index 0000000..806c9b9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir @@ -0,0 +1,116 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=HasF64 %s +# RUN: llc -mtriple=riscv32 -mattr=+Zve64x -run-pass=legalizer %s -o - | FileCheck --check-prefix=NoF64 %s + +--- +name: splatvector_nxv1i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv1i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF1]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>) + ; HasF64-NEXT: PseudoRET implicit $v8 + ; + ; NoF64-LABEL: name: splatvector_nxv1i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0 + ; NoF64-NEXT: [[DEF2:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF2]], [[DEF]](s32), [[DEF1]], $x0 + ; NoF64-NEXT: $v8 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 1 x s64>) + ; NoF64-NEXT: PseudoRET implicit $v8 + %0:_(s64) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR %0(s64) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: splatvector_nxv2i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv2i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF1]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>) + ; HasF64-NEXT: PseudoRET implicit $v8m2 + ; + ; NoF64-LABEL: name: splatvector_nxv2i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0 + ; NoF64-NEXT: [[DEF2:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF2]], [[DEF]](s32), [[DEF1]], $x0 + ; NoF64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 2 x s64>) + ; NoF64-NEXT: PseudoRET implicit $v8m2 + %0:_(s64) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %0(s64) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: splatvector_nxv4i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv4i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF1]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>) + ; HasF64-NEXT: PseudoRET implicit $v8m4 + ; + ; NoF64-LABEL: name: splatvector_nxv4i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0 + ; NoF64-NEXT: [[DEF2:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF2]], [[DEF]](s32), [[DEF1]], $x0 + ; NoF64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 4 x s64>) + ; NoF64-NEXT: PseudoRET implicit $v8m4 + %0:_(s64) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR %0(s64) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: splatvector_nxv8i64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + ; HasF64-LABEL: name: splatvector_nxv8i64 + ; HasF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; HasF64-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[DEF]](s32), [[DEF1]](s32) + ; HasF64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; HasF64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>) + ; HasF64-NEXT: PseudoRET implicit $v8m8 + ; + ; NoF64-LABEL: name: splatvector_nxv8i64 + ; NoF64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0 + ; NoF64-NEXT: [[DEF2:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF + ; NoF64-NEXT: [[SPLAT_VECTOR_SPLIT_I64_VL:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR_SPLIT_I64_VL [[DEF2]], [[DEF]](s32), [[DEF1]], $x0 + ; NoF64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR_SPLIT_I64_VL]](<vscale x 8 x s64>) + ; NoF64-NEXT: PseudoRET implicit $v8m8 + %0:_(s64) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR %0(s64) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir index 4de02b1..8a34521 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir @@ -9,8 +9,8 @@ body: | ; CHECK-LABEL: name: test_nxv1i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 1 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 1 x s8>) = COPY $v8 %1:_(<vscale x 1 x s8>) = COPY $v9 @@ -27,8 +27,8 @@ body: | ; CHECK-LABEL: name: test_nxv2i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 2 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 2 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 2 x s8>) = COPY $v8 %1:_(<vscale x 2 x s8>) = COPY $v9 @@ -45,8 +45,8 @@ body: | ; CHECK-LABEL: name: test_nxv4i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 4 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 4 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 4 x s8>) = COPY $v8 %1:_(<vscale x 4 x s8>) = COPY $v9 @@ -63,8 +63,8 @@ body: | ; CHECK-LABEL: name: test_nxv8i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 8 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 8 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 8 x s8>) = COPY $v8 %1:_(<vscale x 8 x s8>) = COPY $v9 @@ -81,8 +81,8 @@ body: | ; CHECK-LABEL: name: test_nxv16i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v10m2 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 16 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]](<vscale x 16 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8m2 %0:_(<vscale x 16 x s8>) = COPY $v8m2 %1:_(<vscale x 16 x s8>) = COPY $v10m2 @@ -99,8 +99,8 @@ body: | ; CHECK-LABEL: name: test_nxv32i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v12m4 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 32 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]](<vscale x 32 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8m4 %0:_(<vscale x 32 x s8>) = COPY $v8m4 %1:_(<vscale x 32 x s8>) = COPY $v12m4 @@ -117,8 +117,8 @@ body: | ; CHECK-LABEL: name: test_nxv64i8 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v16m8 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 64 x s8>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]](<vscale x 64 x s8>) ; CHECK-NEXT: PseudoRET implicit $v8m8 %0:_(<vscale x 64 x s8>) = COPY $v8m8 %1:_(<vscale x 64 x s8>) = COPY $v16m8 @@ -135,8 +135,8 @@ body: | ; CHECK-LABEL: name: test_nxv1i16 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s16>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 1 x s16>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 1 x s16>) = COPY $v8 %1:_(<vscale x 1 x s16>) = COPY $v9 @@ -153,8 +153,8 @@ body: | ; CHECK-LABEL: name: test_nxv2i16 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 2 x s16>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 2 x s16>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 2 x s16>) = COPY $v8 %1:_(<vscale x 2 x s16>) = COPY $v9 @@ -171,8 +171,8 @@ body: | ; CHECK-LABEL: name: test_nxv4i16 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 4 x s16>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 4 x s16>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 4 x s16>) = COPY $v8 %1:_(<vscale x 4 x s16>) = COPY $v9 @@ -189,8 +189,8 @@ body: | ; CHECK-LABEL: name: test_nxv8i16 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v10m2 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 8 x s16>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]](<vscale x 8 x s16>) ; CHECK-NEXT: PseudoRET implicit $v8m2 %0:_(<vscale x 8 x s16>) = COPY $v8m2 %1:_(<vscale x 8 x s16>) = COPY $v10m2 @@ -207,8 +207,8 @@ body: | ; CHECK-LABEL: name: test_nxv16i16 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v12m4 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 16 x s16>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]](<vscale x 16 x s16>) ; CHECK-NEXT: PseudoRET implicit $v8m4 %0:_(<vscale x 16 x s16>) = COPY $v8m4 %1:_(<vscale x 16 x s16>) = COPY $v12m4 @@ -225,8 +225,8 @@ body: | ; CHECK-LABEL: name: test_nxv32i16 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v16m8 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 32 x s16>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]](<vscale x 32 x s16>) ; CHECK-NEXT: PseudoRET implicit $v8m8 %0:_(<vscale x 32 x s16>) = COPY $v8m8 %1:_(<vscale x 32 x s16>) = COPY $v16m8 @@ -243,8 +243,8 @@ body: | ; CHECK-LABEL: name: test_nxv1i32 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s32>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 1 x s32>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 1 x s32>) = COPY $v8 %1:_(<vscale x 1 x s32>) = COPY $v9 @@ -261,8 +261,8 @@ body: | ; CHECK-LABEL: name: test_nxv2i32 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 2 x s32>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 2 x s32>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 2 x s32>) = COPY $v8 %1:_(<vscale x 2 x s32>) = COPY $v9 @@ -279,8 +279,8 @@ body: | ; CHECK-LABEL: name: test_nxv4i32 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v10m2 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 4 x s32>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]](<vscale x 4 x s32>) ; CHECK-NEXT: PseudoRET implicit $v8m2 %0:_(<vscale x 4 x s32>) = COPY $v8m2 %1:_(<vscale x 4 x s32>) = COPY $v10m2 @@ -297,8 +297,8 @@ body: | ; CHECK-LABEL: name: test_nxv8i32 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v12m4 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 8 x s32>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]](<vscale x 8 x s32>) ; CHECK-NEXT: PseudoRET implicit $v8m4 %0:_(<vscale x 8 x s32>) = COPY $v8m4 %1:_(<vscale x 8 x s32>) = COPY $v12m4 @@ -315,8 +315,8 @@ body: | ; CHECK-LABEL: name: test_nxv16i32 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v16m8 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 16 x s32>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]](<vscale x 16 x s32>) ; CHECK-NEXT: PseudoRET implicit $v8m8 %0:_(<vscale x 16 x s32>) = COPY $v8m8 %1:_(<vscale x 16 x s32>) = COPY $v16m8 @@ -333,8 +333,8 @@ body: | ; CHECK-LABEL: name: test_nxv1i64 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v9 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s64>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8 = COPY [[XOR]](<vscale x 1 x s64>) ; CHECK-NEXT: PseudoRET implicit $v8 %0:_(<vscale x 1 x s64>) = COPY $v8 %1:_(<vscale x 1 x s64>) = COPY $v9 @@ -351,8 +351,8 @@ body: | ; CHECK-LABEL: name: test_nxv2i64 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v10m2 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 2 x s64>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m2 = COPY [[XOR]](<vscale x 2 x s64>) ; CHECK-NEXT: PseudoRET implicit $v8m2 %0:_(<vscale x 2 x s64>) = COPY $v8m2 %1:_(<vscale x 2 x s64>) = COPY $v10m2 @@ -369,8 +369,8 @@ body: | ; CHECK-LABEL: name: test_nxv4i64 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v12m4 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 4 x s64>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m4 = COPY [[XOR]](<vscale x 4 x s64>) ; CHECK-NEXT: PseudoRET implicit $v8m4 %0:_(<vscale x 4 x s64>) = COPY $v8m4 %1:_(<vscale x 4 x s64>) = COPY $v12m4 @@ -387,8 +387,8 @@ body: | ; CHECK-LABEL: name: test_nxv8i64 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v16m8 - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_XOR [[COPY]], [[COPY1]] - ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 8 x s64>) + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_XOR [[COPY]], [[COPY1]] + ; CHECK-NEXT: $v8m8 = COPY [[XOR]](<vscale x 8 x s64>) ; CHECK-NEXT: PseudoRET implicit $v8m8 %0:_(<vscale x 8 x s64>) = COPY $v8m8 %1:_(<vscale x 8 x s64>) = COPY $v16m8 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir new file mode 100644 index 0000000..fe4ddfa --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir @@ -0,0 +1,1589 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV32 %s +# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck --check-prefix=RV64 %s + +# Extend from s1 element vectors +--- +name: zext_nxv1i8_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i8_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i8_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v8 + %0:_(<vscale x 1 x s8>) = G_ZEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s8>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i16_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i16_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i16_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v8 + %0:_(<vscale x 1 x s16>) = G_ZEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s16>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i32_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i32_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i32_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_ZEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i64_nxv1i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SELECT [[COPY]](<vscale x 1 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s1>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ZEXT %1(<vscale x 1 x s1>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i8_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i8_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i8_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v8 + %0:_(<vscale x 2 x s8>) = G_ZEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s8>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i16_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i16_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i16_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v8 + %0:_(<vscale x 2 x s16>) = G_ZEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s16>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i32_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i32_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i32_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s1>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_ZEXT %1(<vscale x 2 x s1>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SELECT [[COPY]](<vscale x 2 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s1>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ZEXT %1(<vscale x 2 x s1>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i8_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i8_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv4i8_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s1>) = COPY $v8 + %0:_(<vscale x 4 x s8>) = G_ZEXT %1(<vscale x 4 x s1>) + $v8 = COPY %0(<vscale x 4 x s8>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv4i16_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i16_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv4i16_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 4 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s1>) = COPY $v8 + %0:_(<vscale x 4 x s16>) = G_ZEXT %1(<vscale x 4 x s1>) + $v8 = COPY %0(<vscale x 4 x s16>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv4i32_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i32_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv4i32_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s1>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_ZEXT %1(<vscale x 4 x s1>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s1>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_ZEXT %1(<vscale x 4 x s1>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i8_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i8_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8 = COPY [[SELECT]](<vscale x 8 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv8i8_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8 = COPY [[SELECT]](<vscale x 8 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 8 x s1>) = COPY $v8 + %0:_(<vscale x 8 x s8>) = G_ZEXT %1(<vscale x 8 x s1>) + $v8 = COPY %0(<vscale x 8 x s8>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv8i16_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i16_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 8 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv8i16_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 8 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 8 x s1>) = COPY $v8 + %0:_(<vscale x 8 x s16>) = G_ZEXT %1(<vscale x 8 x s1>) + $v8m2 = COPY %0(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv8i32_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i32_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv8i32_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s1>) = COPY $v8 + %0:_(<vscale x 8 x s32>) = G_ZEXT %1(<vscale x 8 x s1>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV]](s64) + ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C3]](s32) + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV1]](s64) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s1>) = COPY $v8 + %0:_(<vscale x 8 x s64>) = G_ZEXT %1(<vscale x 8 x s1>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv16i8_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i8_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 16 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv16i8_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m2 = COPY [[SELECT]](<vscale x 16 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 16 x s1>) = COPY $v8 + %0:_(<vscale x 16 x s8>) = G_ZEXT %1(<vscale x 16 x s1>) + $v8m2 = COPY %0(<vscale x 16 x s8>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv16i16_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i16_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 16 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv16i16_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 16 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 16 x s1>) = COPY $v8 + %0:_(<vscale x 16 x s16>) = G_ZEXT %1(<vscale x 16 x s1>) + $v8m4 = COPY %0(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv16i32_nxv16i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i32_nxv16i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv16i32_nxv16i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SELECT [[COPY]](<vscale x 16 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s1>) = COPY $v8 + %0:_(<vscale x 16 x s32>) = G_ZEXT %1(<vscale x 16 x s1>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv32i8_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv32i8_nxv32i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 32 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv32i8_nxv32i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m4 = COPY [[SELECT]](<vscale x 32 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 32 x s1>) = COPY $v8 + %0:_(<vscale x 32 x s8>) = G_ZEXT %1(<vscale x 32 x s1>) + $v8m4 = COPY %0(<vscale x 32 x s8>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv32i16_nxv32i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv32i16_nxv32i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 32 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv32i16_nxv32i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SELECT [[COPY]](<vscale x 32 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 32 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 32 x s1>) = COPY $v8 + %0:_(<vscale x 32 x s16>) = G_ZEXT %1(<vscale x 32 x s1>) + $v8m8 = COPY %0(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv64i8_nxv64i1 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv64i8_nxv64i1 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8 + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32) + ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[COPY]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV32-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 64 x s8>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv64i8_nxv64i1 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8 + ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT]](s64) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV64-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[ANYEXT1]](s64) + ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[COPY]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]] + ; RV64-NEXT: $v8m8 = COPY [[SELECT]](<vscale x 64 x s8>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 64 x s1>) = COPY $v8 + %0:_(<vscale x 64 x s8>) = G_ZEXT %1(<vscale x 64 x s1>) + $v8m8 = COPY %0(<vscale x 64 x s8>) + PseudoRET implicit $v8m8 +... + +# Extend from s8 element vectors +--- +name: zext_nxv1i16_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s16>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s16>) = G_ZEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s16>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i32_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_ZEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i64_nxv1i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s8>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ZEXT %1(<vscale x 1 x s8>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i16_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s16>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s16>) = G_ZEXT %1(<vscale x 2 x s8>) + $v8 = COPY %0(<vscale x 2 x s16>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i32_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_ZEXT %1(<vscale x 2 x s8>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s8>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ZEXT %1(<vscale x 2 x s8>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i16_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 4 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s16>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 4 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s16>) = G_ZEXT %1(<vscale x 4 x s8>) + $v8 = COPY %0(<vscale x 4 x s16>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv4i32_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_ZEXT %1(<vscale x 4 x s8>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s8>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_ZEXT %1(<vscale x 4 x s8>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i16_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 8 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s16>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 8 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s16>) = G_ZEXT %1(<vscale x 8 x s8>) + $v8m2 = COPY %0(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv8i32_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s32>) = G_ZEXT %1(<vscale x 8 x s8>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s8>) = COPY $v8 + %0:_(<vscale x 8 x s64>) = G_ZEXT %1(<vscale x 8 x s8>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv16i16_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 16 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 16 x s16>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 16 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 16 x s8>) = COPY $v8m2 + %0:_(<vscale x 16 x s16>) = G_ZEXT %1(<vscale x 16 x s8>) + $v8m4 = COPY %0(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv16i32_nxv16i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s8>) = COPY $v8m2 + %0:_(<vscale x 16 x s32>) = G_ZEXT %1(<vscale x 16 x s8>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv32i16_nxv32i8 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_ZEXT [[COPY]](<vscale x 32 x s8>) + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 32 x s16>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 32 x s16>) = G_ZEXT [[COPY]](<vscale x 32 x s8>) + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 32 x s16>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 32 x s8>) = COPY $v8m4 + %0:_(<vscale x 32 x s16>) = G_ZEXT %1(<vscale x 32 x s8>) + $v8m8 = COPY %0(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 +... + +# Extend from s16 element vectors +--- +name: zext_nxv1i32_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s16>) = COPY $v8 + %0:_(<vscale x 1 x s32>) = G_ZEXT %1(<vscale x 1 x s16>) + $v8 = COPY %0(<vscale x 1 x s32>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv1i64_nxv1i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s16>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ZEXT %1(<vscale x 1 x s16>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i32_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 2 x s16>) = COPY $v8 + %0:_(<vscale x 2 x s32>) = G_ZEXT %1(<vscale x 2 x s16>) + $v8 = COPY %0(<vscale x 2 x s32>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s16>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ZEXT %1(<vscale x 2 x s16>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i32_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 4 x s16>) = COPY $v8 + %0:_(<vscale x 4 x s32>) = G_ZEXT %1(<vscale x 4 x s16>) + $v8m2 = COPY %0(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s16>) = COPY $v8 + %0:_(<vscale x 4 x s64>) = G_ZEXT %1(<vscale x 4 x s16>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i32_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 8 x s16>) = COPY $v8m2 + %0:_(<vscale x 8 x s32>) = G_ZEXT %1(<vscale x 8 x s16>) + $v8m4 = COPY %0(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s16>) = COPY $v8m4 + %0:_(<vscale x 8 x s64>) = G_ZEXT %1(<vscale x 8 x s16>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... +--- +name: zext_nxv16i32_nxv16i16 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s16>) + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s16>) + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 16 x s16>) = COPY $v8m4 + %0:_(<vscale x 16 x s32>) = G_ZEXT %1(<vscale x 16 x s16>) + $v8m8 = COPY %0(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 +... + +# Extend from s32 element vectors +--- +name: zext_nxv1i64_nxv1i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s32>) + ; RV32-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s32>) + ; RV64-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8 + %1:_(<vscale x 1 x s32>) = COPY $v8 + %0:_(<vscale x 1 x s64>) = G_ZEXT %1(<vscale x 1 x s32>) + $v8 = COPY %0(<vscale x 1 x s64>) + PseudoRET implicit $v8 +... +--- +name: zext_nxv2i64_nxv2i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s32>) + ; RV32-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s32>) + ; RV64-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m2 + %1:_(<vscale x 2 x s32>) = COPY $v8 + %0:_(<vscale x 2 x s64>) = G_ZEXT %1(<vscale x 2 x s32>) + $v8m2 = COPY %0(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 +... +--- +name: zext_nxv4i64_nxv4i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s32>) + ; RV32-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s32>) + ; RV64-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m4 + %1:_(<vscale x 4 x s32>) = COPY $v8m2 + %0:_(<vscale x 4 x s64>) = G_ZEXT %1(<vscale x 4 x s32>) + $v8m4 = COPY %0(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 +... +--- +name: zext_nxv8i64_nxv8i32 +legalized: false +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + ; RV32-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV32: liveins: $v8 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 + ; RV32-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s32>) + ; RV32-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV64: liveins: $v8 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s32>) + ; RV64-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV64-NEXT: PseudoRET implicit $v8m8 + %1:_(<vscale x 8 x s32>) = COPY $v8m4 + %0:_(<vscale x 8 x s64>) = G_ZEXT %1(<vscale x 8 x s32>) + $v8m8 = COPY %0(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir new file mode 100644 index 0000000..062179c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir @@ -0,0 +1,820 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: anyext_nxv1i16_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s16>) = G_ANYEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i32_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s32>) = G_ANYEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_ANYEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i16_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s16>) = G_ANYEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s32>) = G_ANYEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_ANYEXT %0(<vscale x 2 x s8>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i16_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 4 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 4 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s16>) = G_ANYEXT %0(<vscale x 4 x s8>) + $v8 = COPY %1(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv4i32_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s32>) = G_ANYEXT %0(<vscale x 4 x s8>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s64>) = G_ANYEXT %0(<vscale x 4 x s8>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i16_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 8 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 8 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s16>) = G_ANYEXT %0(<vscale x 8 x s8>) + $v8m2 = COPY %1(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv8i32_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s32>) = G_ANYEXT %0(<vscale x 8 x s8>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s64>) = G_ANYEXT %0(<vscale x 8 x s8>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i16_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 16 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 16 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 16 x s8>) = COPY $v8m2 + %1:_(<vscale x 16 x s16>) = G_ANYEXT %0(<vscale x 16 x s8>) + $v8m4 = COPY %1(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv16i32_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m4 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m4 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s8>) = COPY $v8m4 + %1:_(<vscale x 16 x s32>) = G_ANYEXT %0(<vscale x 16 x s8>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv32i16_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ANYEXT [[COPY]](<vscale x 32 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 32 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ANYEXT [[COPY]](<vscale x 32 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 32 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 32 x s8>) = COPY $v8m4 + %1:_(<vscale x 32 x s16>) = G_ANYEXT %0(<vscale x 32 x s8>) + $v8m8 = COPY %1(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i32_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = COPY $v8 + %1:_(<vscale x 1 x s32>) = G_ANYEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv1i64_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s16>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_ANYEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i32_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 2 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s16>) = COPY $v8 + %1:_(<vscale x 2 x s32>) = G_ANYEXT %0(<vscale x 2 x s16>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV32I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s16>) + ; RV64I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s16>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_ANYEXT %0(<vscale x 2 x s16>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i32_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV32I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV64I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 4 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s16>) = COPY $v8 + %1:_(<vscale x 4 x s32>) = G_ANYEXT %0(<vscale x 4 x s16>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV32I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s16>) + ; RV64I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s16>) = COPY $v8 + %1:_(<vscale x 4 x s64>) = G_ANYEXT %0(<vscale x 4 x s16>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i32_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV32I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV64I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 8 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s16>) = COPY $v8m2 + %1:_(<vscale x 8 x s32>) = G_ANYEXT %0(<vscale x 8 x s16>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV32I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s16>) + ; RV64I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s16>) = COPY $v8m2 + %1:_(<vscale x 8 x s64>) = G_ANYEXT %0(<vscale x 8 x s16>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv16i32_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s16>) + ; RV32I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ANYEXT [[COPY]](<vscale x 16 x s16>) + ; RV64I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 16 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s16>) = COPY $v8m4 + %1:_(<vscale x 16 x s32>) = G_ANYEXT %0(<vscale x 16 x s16>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: anyext_nxv1i64_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s32>) + ; RV32I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: anyext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ANYEXT [[COPY]](<vscale x 1 x s32>) + ; RV64I-NEXT: $v8 = COPY [[ANYEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s32>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_ANYEXT %0(<vscale x 1 x s32>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: anyext_nxv2i64_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s32>) + ; RV32I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: anyext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ANYEXT [[COPY]](<vscale x 2 x s32>) + ; RV64I-NEXT: $v8m2 = COPY [[ANYEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s32>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_ANYEXT %0(<vscale x 2 x s32>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: anyext_nxv4i64_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s32>) + ; RV32I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: anyext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ANYEXT [[COPY]](<vscale x 4 x s32>) + ; RV64I-NEXT: $v8m4 = COPY [[ANYEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s32>) = COPY $v8m2 + %1:_(<vscale x 4 x s64>) = G_ANYEXT %0(<vscale x 4 x s32>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: anyext_nxv8i64_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4 + ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s32>) + ; RV32I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: anyext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ANYEXT [[COPY]](<vscale x 8 x s32>) + ; RV64I-NEXT: $v8m8 = COPY [[ANYEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s32>) = COPY $v8m4 + %1:_(<vscale x 8 x s64>) = G_ANYEXT %0(<vscale x 8 x s32>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir new file mode 100644 index 0000000..925d6ae --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir @@ -0,0 +1,675 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: icmp_nxv1i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 1 x s1>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 2 x s1>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s1>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 8 x s1>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 16 x s1>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 32 x s1>), %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv64i1 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv64i1 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s1>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv64i1 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s1>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF + %1:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 64 x s1>), %0 + $v8 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 1 x s8>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 2 x s8>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s8>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 8 x s8>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 16 x s8>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 32 x s8>), %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv64i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv64i8 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s8>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv64i8 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 64 x s8>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 64 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF + %1:_(<vscale x 64 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 64 x s8>), %0 + $v8 = COPY %1(<vscale x 64 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i16 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s16>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i16 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s16>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 1 x s16>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i16 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s16>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i16 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s16>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 2 x s16>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i16 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s16>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i16 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s16>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s16>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i16 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s16>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i16 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s16>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 8 x s16>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i16 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s16>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i16 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s16>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 16 x s16>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv32i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv32i16 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s16>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv32i16 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 32 x s16>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 32 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF + %1:_(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 32 x s16>), %0 + $v8 = COPY %1(<vscale x 32 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i32 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s32>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i32 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s32>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 1 x s32>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i32 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s32>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i32 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s32>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 2 x s32>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i32 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s32>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i32 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s32>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s32>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i32 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s32>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i32 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s32>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 8 x s32>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv16i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv16i32 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s32>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv16i32 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 16 x s32>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 16 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF + %1:_(<vscale x 16 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 16 x s32>), %0 + $v8 = COPY %1(<vscale x 16 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv1i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv1i64 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s64>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv1i64 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x s64>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 1 x s64>), %0 + $v8 = COPY %1(<vscale x 1 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv2i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv2i64 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s64>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv2i64 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 2 x s64>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 2 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 2 x s64>), %0 + $v8 = COPY %1(<vscale x 2 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv4i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv4i64 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s64>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv4i64 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 4 x s64>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s64>), %0 + $v8 = COPY %1(<vscale x 4 x s1>) + PseudoRET implicit $v8 + +... +--- +name: icmp_nxv8i64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; RV32I-LABEL: name: icmp_nxv8i64 + ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF + ; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s64>), [[DEF]] + ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: icmp_nxv8i64 + ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF + ; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 8 x s64>), [[DEF]] + ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF + %1:_(<vscale x 8 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 8 x s64>), %0 + $v8 = COPY %1(<vscale x 8 x s1>) + PseudoRET implicit $v8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir new file mode 100644 index 0000000..a754b8b --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir @@ -0,0 +1,820 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: sext_nxv1i16_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s16>) = G_SEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i32_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s32>) = G_SEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_SEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i16_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s16>) = G_SEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s32>) = G_SEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_SEXT %0(<vscale x 2 x s8>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i16_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 4 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 4 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s16>) = G_SEXT %0(<vscale x 4 x s8>) + $v8 = COPY %1(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv4i32_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s32>) = G_SEXT %0(<vscale x 4 x s8>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s64>) = G_SEXT %0(<vscale x 4 x s8>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i16_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 8 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 8 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s16>) = G_SEXT %0(<vscale x 8 x s8>) + $v8m2 = COPY %1(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv8i32_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s32>) = G_SEXT %0(<vscale x 8 x s8>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s64>) = G_SEXT %0(<vscale x 8 x s8>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i16_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 16 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 16 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 16 x s8>) = COPY $v8m2 + %1:_(<vscale x 16 x s16>) = G_SEXT %0(<vscale x 16 x s8>) + $v8m4 = COPY %1(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv16i32_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s8>) = COPY $v8m2 + %1:_(<vscale x 16 x s32>) = G_SEXT %0(<vscale x 16 x s8>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv32i16_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SEXT [[COPY]](<vscale x 32 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 32 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SEXT [[COPY]](<vscale x 32 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 32 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 32 x s8>) = COPY $v8m4 + %1:_(<vscale x 32 x s16>) = G_SEXT %0(<vscale x 32 x s8>) + $v8m8 = COPY %1(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i32_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = COPY $v8 + %1:_(<vscale x 1 x s32>) = G_SEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv1i64_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s16>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_SEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i32_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 2 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s16>) = COPY $v8 + %1:_(<vscale x 2 x s32>) = G_SEXT %0(<vscale x 2 x s16>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV32I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s16>) + ; RV64I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s16>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_SEXT %0(<vscale x 2 x s16>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i32_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV32I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV64I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 4 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s16>) = COPY $v8 + %1:_(<vscale x 4 x s32>) = G_SEXT %0(<vscale x 4 x s16>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV32I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s16>) + ; RV64I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s16>) = COPY $v8 + %1:_(<vscale x 4 x s64>) = G_SEXT %0(<vscale x 4 x s16>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i32_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV32I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV64I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 8 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s16>) = COPY $v8m2 + %1:_(<vscale x 8 x s32>) = G_SEXT %0(<vscale x 8 x s16>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV32I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s16>) + ; RV64I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s16>) = COPY $v8m2 + %1:_(<vscale x 8 x s64>) = G_SEXT %0(<vscale x 8 x s16>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv16i32_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s16>) + ; RV32I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SEXT [[COPY]](<vscale x 16 x s16>) + ; RV64I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 16 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s16>) = COPY $v8m4 + %1:_(<vscale x 16 x s32>) = G_SEXT %0(<vscale x 16 x s16>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: sext_nxv1i64_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s32>) + ; RV32I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: sext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SEXT [[COPY]](<vscale x 1 x s32>) + ; RV64I-NEXT: $v8 = COPY [[SEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s32>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_SEXT %0(<vscale x 1 x s32>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: sext_nxv2i64_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s32>) + ; RV32I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: sext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SEXT [[COPY]](<vscale x 2 x s32>) + ; RV64I-NEXT: $v8m2 = COPY [[SEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s32>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_SEXT %0(<vscale x 2 x s32>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: sext_nxv4i64_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s32>) + ; RV32I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: sext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SEXT [[COPY]](<vscale x 4 x s32>) + ; RV64I-NEXT: $v8m4 = COPY [[SEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s32>) = COPY $v8m2 + %1:_(<vscale x 4 x s64>) = G_SEXT %0(<vscale x 4 x s32>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: sext_nxv8i64_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4 + ; RV32I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s32>) + ; RV32I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: sext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4 + ; RV64I-NEXT: [[SEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SEXT [[COPY]](<vscale x 8 x s32>) + ; RV64I-NEXT: $v8m8 = COPY [[SEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s32>) = COPY $v8m4 + %1:_(<vscale x 8 x s64>) = G_SEXT %0(<vscale x 8 x s32>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir new file mode 100644 index 0000000..c3bc4a9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir @@ -0,0 +1,820 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck -check-prefix=RV64I %s + +--- +name: zext_nxv1i16_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i16_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s16>) = G_ZEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s16>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i32_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i32_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s8>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s8>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i16_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i16_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s16>) = G_ZEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s16>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i32_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s8>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s8>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s8>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i16_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 4 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv4i16_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 4 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s16>) = G_ZEXT %0(<vscale x 4 x s8>) + $v8 = COPY %1(<vscale x 4 x s16>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv4i32_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv4i32_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s8>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s8>) = COPY $v8 + %1:_(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s8>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i16_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 8 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv8i16_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 8 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s16>) = G_ZEXT %0(<vscale x 8 x s8>) + $v8m2 = COPY %1(<vscale x 8 x s16>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv8i32_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv8i32_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s8>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s8>) = COPY $v8 + %1:_(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s8>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i16_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 16 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv16i16_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 16 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 16 x s8>) = COPY $v8m2 + %1:_(<vscale x 16 x s16>) = G_ZEXT %0(<vscale x 16 x s8>) + $v8m4 = COPY %1(<vscale x 16 x s16>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv16i32_nxv16i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv16i32_nxv16i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s8>) = COPY $v8m2 + %1:_(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s8>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv32i16_nxv32i8 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ZEXT [[COPY]](<vscale x 32 x s8>) + ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 32 x s16>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv32i16_nxv32i8 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ZEXT [[COPY]](<vscale x 32 x s8>) + ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 32 x s16>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 32 x s8>) = COPY $v8m4 + %1:_(<vscale x 32 x s16>) = G_ZEXT %0(<vscale x 32 x s8>) + $v8m8 = COPY %1(<vscale x 32 x s16>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i32_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i32_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = COPY $v8 + %1:_(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv1i64_nxv1i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s16>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s16>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s16>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i32_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv2i32_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 2 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 2 x s16>) = COPY $v8 + %1:_(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s16>) + $v8 = COPY %1(<vscale x 2 x s32>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s16>) + ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s16>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s16>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i32_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv4i32_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 4 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 4 x s16>) = COPY $v8 + %1:_(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s16>) + $v8m2 = COPY %1(<vscale x 4 x s32>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s16>) + ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s16>) = COPY $v8 + %1:_(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s16>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i32_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv8i32_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 8 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 8 x s16>) = COPY $v8m2 + %1:_(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s16>) + $v8m4 = COPY %1(<vscale x 8 x s32>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m4 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m4 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s16>) + ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s16>) = COPY $v8m4 + %1:_(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s16>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv16i32_nxv16i16 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s16>) + ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv16i32_nxv16i16 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ZEXT [[COPY]](<vscale x 16 x s16>) + ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 16 x s32>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 16 x s16>) = COPY $v8m4 + %1:_(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s16>) + $v8m8 = COPY %1(<vscale x 16 x s32>) + PseudoRET implicit $v8m8 + +... +--- +name: zext_nxv1i64_nxv1i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s32>) + ; RV32I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8 + ; + ; RV64I-LABEL: name: zext_nxv1i64_nxv1i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ZEXT [[COPY]](<vscale x 1 x s32>) + ; RV64I-NEXT: $v8 = COPY [[ZEXT]](<vscale x 1 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8 + %0:_(<vscale x 1 x s32>) = COPY $v8 + %1:_(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s32>) + $v8 = COPY %1(<vscale x 1 x s64>) + PseudoRET implicit $v8 + +... +--- +name: zext_nxv2i64_nxv2i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s32>) + ; RV32I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64I-LABEL: name: zext_nxv2i64_nxv2i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ZEXT [[COPY]](<vscale x 2 x s32>) + ; RV64I-NEXT: $v8m2 = COPY [[ZEXT]](<vscale x 2 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m2 + %0:_(<vscale x 2 x s32>) = COPY $v8 + %1:_(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s32>) + $v8m2 = COPY %1(<vscale x 2 x s64>) + PseudoRET implicit $v8m2 + +... +--- +name: zext_nxv4i64_nxv4i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s32>) + ; RV32I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64I-LABEL: name: zext_nxv4i64_nxv4i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ZEXT [[COPY]](<vscale x 4 x s32>) + ; RV64I-NEXT: $v8m4 = COPY [[ZEXT]](<vscale x 4 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m4 + %0:_(<vscale x 4 x s32>) = COPY $v8m2 + %1:_(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s32>) + $v8m4 = COPY %1(<vscale x 4 x s64>) + PseudoRET implicit $v8m4 + +... +--- +name: zext_nxv8i64_nxv8i32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $v8 + + ; RV32I-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV32I: liveins: $v8 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4 + ; RV32I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s32>) + ; RV32I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV32I-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64I-LABEL: name: zext_nxv8i64_nxv8i32 + ; RV64I: liveins: $v8 + ; RV64I-NEXT: {{ $}} + ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4 + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ZEXT [[COPY]](<vscale x 8 x s32>) + ; RV64I-NEXT: $v8m8 = COPY [[ZEXT]](<vscale x 8 x s64>) + ; RV64I-NEXT: PseudoRET implicit $v8m8 + %0:_(<vscale x 8 x s32>) = COPY $v8m4 + %1:_(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s32>) + $v8m8 = COPY %1(<vscale x 8 x s64>) + PseudoRET implicit $v8m8 + +... diff --git a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll index bafa92e..65d0768 100644 --- a/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll +++ b/llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll @@ -18,14 +18,12 @@ define i32 @ctz_nxv4i32(<vscale x 4 x i32> %a) #0 { ; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV32-NEXT: vmv.v.i v8, 0 -; RV32-NEXT: vmerge.vim v8, v8, -1, v0 -; RV32-NEXT: vand.vv v8, v11, v8 +; RV32-NEXT: vmerge.vvm v8, v8, v11, v0 ; RV32-NEXT: vredmaxu.vs v8, v8, v8 ; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: sub a0, a0, a1 -; RV32-NEXT: lui a1, 16 -; RV32-NEXT: addi a1, a1, -1 -; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: slli a0, a0, 16 +; RV32-NEXT: srli a0, a0, 16 ; RV32-NEXT: ret ; ; RV64-LABEL: ctz_nxv4i32: @@ -41,14 +39,12 @@ define i32 @ctz_nxv4i32(<vscale x 4 x i32> %a) #0 { ; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64-NEXT: vmv.v.i v8, 0 -; RV64-NEXT: vmerge.vim v8, v8, -1, v0 -; RV64-NEXT: vand.vv v8, v11, v8 +; RV64-NEXT: vmerge.vvm v8, v8, v11, v0 ; RV64-NEXT: vredmaxu.vs v8, v8, v8 ; RV64-NEXT: vmv.x.s a1, v8 -; RV64-NEXT: sub a0, a0, a1 -; RV64-NEXT: lui a1, 16 -; RV64-NEXT: addiw a1, a1, -1 -; RV64-NEXT: and a0, a0, a1 +; RV64-NEXT: subw a0, a0, a1 +; RV64-NEXT: slli a0, a0, 48 +; RV64-NEXT: srli a0, a0, 48 ; RV64-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.nxv4i32(<vscale x 4 x i32> %a, i1 0) ret i32 %res @@ -158,8 +154,7 @@ define i32 @ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) { ; RV64-NEXT: li a1, -1 ; RV64-NEXT: vmadd.vx v16, a1, v8 ; RV64-NEXT: vmv.v.i v8, 0 -; RV64-NEXT: vmerge.vim v8, v8, -1, v0 -; RV64-NEXT: vand.vv v8, v16, v8 +; RV64-NEXT: vmerge.vvm v8, v8, v16, v0 ; RV64-NEXT: vredmaxu.vs v8, v8, v8 ; RV64-NEXT: vmv.x.s a1, v8 ; RV64-NEXT: subw a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll index f5305a1..83d1d1b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll @@ -19,10 +19,9 @@ define <4 x i64> @vwsll_vv_v4i64_sext(<4 x i32> %a, <4 x i32> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_sext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <4 x i32> %a to <4 x i64> %y = sext <4 x i32> %b to <4 x i64> @@ -41,10 +40,9 @@ define <4 x i64> @vwsll_vv_v4i64_zext(<4 x i32> %a, <4 x i32> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <4 x i32> %a to <4 x i64> %y = zext <4 x i32> %b to <4 x i64> @@ -62,9 +60,9 @@ define <4 x i64> @vwsll_vx_i64_v4i64(<4 x i32> %a, i64 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i64_v4i64: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i64> poison, i64 %b, i32 0 %splat = shufflevector <4 x i64> %head, <4 x i64> poison, <4 x i32> zeroinitializer @@ -88,10 +86,8 @@ define <4 x i64> @vwsll_vx_i32_v4i64_sext(<4 x i32> %a, i32 %b) { ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i32> poison, i32 %b, i32 0 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer @@ -116,10 +112,8 @@ define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) { ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i32> poison, i32 %b, i32 0 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer @@ -142,12 +136,9 @@ define <4 x i64> @vwsll_vx_i16_v4i64_sext(<4 x i32> %a, i16 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_sext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf4 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i16> poison, i16 %b, i32 0 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer @@ -170,12 +161,9 @@ define <4 x i64> @vwsll_vx_i16_v4i64_zext(<4 x i32> %a, i16 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i16> poison, i16 %b, i32 0 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer @@ -198,12 +186,9 @@ define <4 x i64> @vwsll_vx_i8_v4i64_sext(<4 x i32> %a, i8 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_sext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i8> poison, i8 %b, i32 0 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer @@ -226,12 +211,9 @@ define <4 x i64> @vwsll_vx_i8_v4i64_zext(<4 x i32> %a, i8 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i8> poison, i8 %b, i32 0 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer @@ -251,9 +233,9 @@ define <4 x i64> @vwsll_vi_v4i64(<4 x i32> %a) { ; ; CHECK-ZVBB-LABEL: vwsll_vi_v4i64: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vi v10, v8, 2 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <4 x i32> %a to <4 x i64> %z = shl <4 x i64> %x, splat (i64 2) @@ -275,10 +257,9 @@ define <8 x i32> @vwsll_vv_v8i32_sext(<8 x i16> %a, <8 x i16> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v8i32_sext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <8 x i16> %a to <8 x i32> %y = sext <8 x i16> %b to <8 x i32> @@ -297,10 +278,9 @@ define <8 x i32> @vwsll_vv_v8i32_zext(<8 x i16> %a, <8 x i16> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v8i32_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <8 x i16> %a to <8 x i32> %y = zext <8 x i16> %b to <8 x i32> @@ -318,9 +298,9 @@ define <8 x i32> @vwsll_vx_i64_v8i32(<8 x i16> %a, i64 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i64_v8i32: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i64> poison, i64 %b, i32 0 %splat = shufflevector <8 x i64> %head, <8 x i64> poison, <8 x i32> zeroinitializer @@ -340,9 +320,9 @@ define <8 x i32> @vwsll_vx_i32_v8i32(<8 x i16> %a, i32 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i32_v8i32: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i32> poison, i32 %b, i32 0 %splat = shufflevector <8 x i32> %head, <8 x i32> poison, <8 x i32> zeroinitializer @@ -366,10 +346,8 @@ define <8 x i32> @vwsll_vx_i16_v8i32_sext(<8 x i16> %a, i16 %b) { ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i16> poison, i16 %b, i32 0 %splat = shufflevector <8 x i16> %head, <8 x i16> poison, <8 x i32> zeroinitializer @@ -394,10 +372,8 @@ define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) { ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i16> poison, i16 %b, i32 0 %splat = shufflevector <8 x i16> %head, <8 x i16> poison, <8 x i32> zeroinitializer @@ -420,12 +396,9 @@ define <8 x i32> @vwsll_vx_i8_v8i32_sext(<8 x i16> %a, i8 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i8_v8i32_sext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf4 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i8> poison, i8 %b, i32 0 %splat = shufflevector <8 x i8> %head, <8 x i8> poison, <8 x i32> zeroinitializer @@ -448,12 +421,9 @@ define <8 x i32> @vwsll_vx_i8_v8i32_zext(<8 x i16> %a, i8 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i8_v8i32_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i8> poison, i8 %b, i32 0 %splat = shufflevector <8 x i8> %head, <8 x i8> poison, <8 x i32> zeroinitializer @@ -473,9 +443,9 @@ define <8 x i32> @vwsll_vi_v8i32(<8 x i16> %a) { ; ; CHECK-ZVBB-LABEL: vwsll_vi_v8i32: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2 +; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vi v10, v8, 2 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <8 x i16> %a to <8 x i32> %z = shl <8 x i32> %x, splat (i32 2) @@ -497,10 +467,9 @@ define <16 x i16> @vwsll_vv_v16i16_sext(<16 x i8> %a, <16 x i8> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v16i16_sext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <16 x i8> %a to <16 x i16> %y = sext <16 x i8> %b to <16 x i16> @@ -519,10 +488,9 @@ define <16 x i16> @vwsll_vv_v16i16_zext(<16 x i8> %a, <16 x i8> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v16i16_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <16 x i8> %a to <16 x i16> %y = zext <16 x i8> %b to <16 x i16> @@ -552,12 +520,9 @@ define <16 x i16> @vwsll_vx_i32_v16i16(<16 x i8> %a, i32 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i32_v16i16: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v12, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vnsrl.wi v8, v12, 0 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8 +; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <16 x i32> poison, i32 %b, i32 0 %splat = shufflevector <16 x i32> %head, <16 x i32> poison, <16 x i32> zeroinitializer @@ -577,9 +542,9 @@ define <16 x i16> @vwsll_vx_i16_v16i16(<16 x i8> %a, i16 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i16_v16i16: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0 +; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <16 x i16> poison, i16 %b, i32 0 %splat = shufflevector <16 x i16> %head, <16 x i16> poison, <16 x i32> zeroinitializer @@ -603,10 +568,8 @@ define <16 x i16> @vwsll_vx_i8_v16i16_sext(<16 x i8> %a, i8 %b) { ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <16 x i8> poison, i8 %b, i32 0 %splat = shufflevector <16 x i8> %head, <16 x i8> poison, <16 x i32> zeroinitializer @@ -631,10 +594,8 @@ define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) { ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <16 x i8> poison, i8 %b, i32 0 %splat = shufflevector <16 x i8> %head, <16 x i8> poison, <16 x i32> zeroinitializer @@ -654,9 +615,9 @@ define <16 x i16> @vwsll_vi_v16i16(<16 x i8> %a) { ; ; CHECK-ZVBB-LABEL: vwsll_vi_v16i16: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf2 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2 +; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVBB-NEXT: vwsll.vi v10, v8, 2 +; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %x = zext <16 x i8> %a to <16 x i16> %z = shl <16 x i16> %x, splat (i16 2) diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-binop-into-select.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binop-into-select.ll new file mode 100644 index 0000000..3a8d08f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fold-binop-into-select.ll @@ -0,0 +1,60 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s + +; The following binop x, (zext i1) tests will be vector-legalized into a vselect +; of two splat_vectors, but on RV64 the splat value will be implicitly +; truncated: +; +; t15: nxv2i32 = splat_vector Constant:i64<1> +; t13: nxv2i32 = splat_vector Constant:i64<0> +; t16: nxv2i32 = vselect t2, t15, t13 +; t7: nxv2i32 = add t4, t16 +; +; Make sure that foldSelectWithIdentityConstant in DAGCombiner.cpp handles the +; truncating splat, so we pull the vselect back and fold it into a mask. + +define <vscale x 2 x i32> @i1_zext_add(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { +; CHECK-LABEL: i1_zext_add: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu +; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t +; CHECK-NEXT: ret + %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> + %add = add <vscale x 2 x i32> %b, %zext + ret <vscale x 2 x i32> %add +} + +define <vscale x 2 x i32> @i1_zext_add_commuted(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { +; CHECK-LABEL: i1_zext_add_commuted: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu +; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t +; CHECK-NEXT: ret + %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> + %add = add <vscale x 2 x i32> %zext, %b + ret <vscale x 2 x i32> %add +} + +define <vscale x 2 x i32> @i1_zext_sub(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { +; CHECK-LABEL: i1_zext_sub: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu +; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> + %sub = sub <vscale x 2 x i32> %b, %zext + ret <vscale x 2 x i32> %sub +} + +define <vscale x 2 x i32> @i1_zext_or(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { +; CHECK-LABEL: i1_zext_or: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu +; CHECK-NEXT: vor.vi v8, v8, 1, v0.t +; CHECK-NEXT: ret + %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> + %or = or <vscale x 2 x i32> %b, %zext + ret <vscale x 2 x i32> %or +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll index e56dca0..a14ce71 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll @@ -149,49 +149,49 @@ define <vscale x 2 x i64> @vwop_vscale_sext_i32i64_multiple_users(ptr %x, ptr %y } define <vscale x 2 x i32> @vwop_vscale_sext_i1i32_multiple_users(ptr %x, ptr %y, ptr %z) { -; RV32-LABEL: vwop_vscale_sext_i1i32_multiple_users: -; RV32: # %bb.0: -; RV32-NEXT: vsetvli a3, zero, e32, m1, ta, mu -; RV32-NEXT: vlm.v v8, (a0) -; RV32-NEXT: vlm.v v9, (a1) -; RV32-NEXT: vlm.v v10, (a2) -; RV32-NEXT: vmv.v.i v11, 0 -; RV32-NEXT: vmv.v.v v0, v8 -; RV32-NEXT: vmerge.vim v12, v11, -1, v0 -; RV32-NEXT: vmv.v.v v0, v9 -; RV32-NEXT: vmerge.vim v9, v11, -1, v0 -; RV32-NEXT: vmv.v.v v0, v10 -; RV32-NEXT: vmerge.vim v10, v11, -1, v0 -; RV32-NEXT: vmul.vv v9, v12, v9 -; RV32-NEXT: li a0, 1 -; RV32-NEXT: vsub.vv v11, v12, v10 -; RV32-NEXT: vmv.v.v v0, v8 -; RV32-NEXT: vsub.vx v10, v10, a0, v0.t -; RV32-NEXT: vor.vv v8, v9, v10 -; RV32-NEXT: vor.vv v8, v8, v11 -; RV32-NEXT: ret +; NO_FOLDING-LABEL: vwop_vscale_sext_i1i32_multiple_users: +; NO_FOLDING: # %bb.0: +; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu +; NO_FOLDING-NEXT: vlm.v v8, (a0) +; NO_FOLDING-NEXT: vlm.v v9, (a1) +; NO_FOLDING-NEXT: vlm.v v10, (a2) +; NO_FOLDING-NEXT: vmv.v.i v11, 0 +; NO_FOLDING-NEXT: vmv.v.v v0, v8 +; NO_FOLDING-NEXT: vmerge.vim v12, v11, -1, v0 +; NO_FOLDING-NEXT: vmv.v.v v0, v9 +; NO_FOLDING-NEXT: vmerge.vim v9, v11, -1, v0 +; NO_FOLDING-NEXT: vmv.v.v v0, v10 +; NO_FOLDING-NEXT: vmerge.vim v10, v11, -1, v0 +; NO_FOLDING-NEXT: vmul.vv v9, v12, v9 +; NO_FOLDING-NEXT: li a0, 1 +; NO_FOLDING-NEXT: vsub.vv v11, v12, v10 +; NO_FOLDING-NEXT: vmv.v.v v0, v8 +; NO_FOLDING-NEXT: vsub.vx v10, v10, a0, v0.t +; NO_FOLDING-NEXT: vor.vv v8, v9, v10 +; NO_FOLDING-NEXT: vor.vv v8, v8, v11 +; NO_FOLDING-NEXT: ret ; -; RV64-LABEL: vwop_vscale_sext_i1i32_multiple_users: -; RV64: # %bb.0: -; RV64-NEXT: vsetvli a3, zero, e32, m1, ta, ma -; RV64-NEXT: vlm.v v8, (a0) -; RV64-NEXT: vlm.v v9, (a1) -; RV64-NEXT: vlm.v v10, (a2) -; RV64-NEXT: vmv.v.i v11, 0 -; RV64-NEXT: vmv.v.v v0, v8 -; RV64-NEXT: vmerge.vim v12, v11, -1, v0 -; RV64-NEXT: vmv.v.v v0, v9 -; RV64-NEXT: vmerge.vim v9, v11, -1, v0 -; RV64-NEXT: vmv.v.v v0, v10 -; RV64-NEXT: vmerge.vim v10, v11, -1, v0 -; RV64-NEXT: vmul.vv v9, v12, v9 -; RV64-NEXT: vmv.v.v v0, v8 -; RV64-NEXT: vmerge.vim v8, v11, 1, v0 -; RV64-NEXT: vsub.vv v8, v10, v8 -; RV64-NEXT: vsub.vv v10, v12, v10 -; RV64-NEXT: vor.vv v8, v9, v8 -; RV64-NEXT: vor.vv v8, v8, v10 -; RV64-NEXT: ret +; FOLDING-LABEL: vwop_vscale_sext_i1i32_multiple_users: +; FOLDING: # %bb.0: +; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu +; FOLDING-NEXT: vlm.v v8, (a0) +; FOLDING-NEXT: vlm.v v9, (a1) +; FOLDING-NEXT: vlm.v v10, (a2) +; FOLDING-NEXT: vmv.v.i v11, 0 +; FOLDING-NEXT: vmv.v.v v0, v8 +; FOLDING-NEXT: vmerge.vim v12, v11, -1, v0 +; FOLDING-NEXT: vmv.v.v v0, v9 +; FOLDING-NEXT: vmerge.vim v9, v11, -1, v0 +; FOLDING-NEXT: vmv.v.v v0, v10 +; FOLDING-NEXT: vmerge.vim v10, v11, -1, v0 +; FOLDING-NEXT: vmul.vv v9, v12, v9 +; FOLDING-NEXT: li a0, 1 +; FOLDING-NEXT: vsub.vv v11, v12, v10 +; FOLDING-NEXT: vmv.v.v v0, v8 +; FOLDING-NEXT: vsub.vx v10, v10, a0, v0.t +; FOLDING-NEXT: vor.vv v8, v9, v10 +; FOLDING-NEXT: vor.vv v8, v8, v11 +; FOLDING-NEXT: ret %a = load <vscale x 2 x i1>, ptr %x %b = load <vscale x 2 x i1>, ptr %y %b2 = load <vscale x 2 x i1>, ptr %z @@ -209,7 +209,7 @@ define <vscale x 2 x i32> @vwop_vscale_sext_i1i32_multiple_users(ptr %x, ptr %y, define <vscale x 2 x i8> @vwop_vscale_sext_i1i8_multiple_users(ptr %x, ptr %y, ptr %z) { ; NO_FOLDING-LABEL: vwop_vscale_sext_i1i8_multiple_users: ; NO_FOLDING: # %bb.0: -; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, ma +; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu ; NO_FOLDING-NEXT: vlm.v v8, (a0) ; NO_FOLDING-NEXT: vlm.v v9, (a1) ; NO_FOLDING-NEXT: vlm.v v10, (a2) @@ -221,17 +221,17 @@ define <vscale x 2 x i8> @vwop_vscale_sext_i1i8_multiple_users(ptr %x, ptr %y, p ; NO_FOLDING-NEXT: vmv1r.v v0, v10 ; NO_FOLDING-NEXT: vmerge.vim v10, v11, -1, v0 ; NO_FOLDING-NEXT: vmul.vv v9, v12, v9 +; NO_FOLDING-NEXT: li a0, 1 +; NO_FOLDING-NEXT: vsub.vv v11, v12, v10 ; NO_FOLDING-NEXT: vmv1r.v v0, v8 -; NO_FOLDING-NEXT: vmerge.vim v8, v11, 1, v0 -; NO_FOLDING-NEXT: vsub.vv v8, v10, v8 -; NO_FOLDING-NEXT: vsub.vv v10, v12, v10 -; NO_FOLDING-NEXT: vor.vv v8, v9, v8 -; NO_FOLDING-NEXT: vor.vv v8, v8, v10 +; NO_FOLDING-NEXT: vsub.vx v10, v10, a0, v0.t +; NO_FOLDING-NEXT: vor.vv v8, v9, v10 +; NO_FOLDING-NEXT: vor.vv v8, v8, v11 ; NO_FOLDING-NEXT: ret ; ; FOLDING-LABEL: vwop_vscale_sext_i1i8_multiple_users: ; FOLDING: # %bb.0: -; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, ma +; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu ; FOLDING-NEXT: vlm.v v8, (a0) ; FOLDING-NEXT: vlm.v v9, (a1) ; FOLDING-NEXT: vlm.v v10, (a2) @@ -243,12 +243,12 @@ define <vscale x 2 x i8> @vwop_vscale_sext_i1i8_multiple_users(ptr %x, ptr %y, p ; FOLDING-NEXT: vmv1r.v v0, v10 ; FOLDING-NEXT: vmerge.vim v10, v11, -1, v0 ; FOLDING-NEXT: vmul.vv v9, v12, v9 +; FOLDING-NEXT: li a0, 1 +; FOLDING-NEXT: vsub.vv v11, v12, v10 ; FOLDING-NEXT: vmv1r.v v0, v8 -; FOLDING-NEXT: vmerge.vim v8, v11, 1, v0 -; FOLDING-NEXT: vsub.vv v8, v10, v8 -; FOLDING-NEXT: vsub.vv v10, v12, v10 -; FOLDING-NEXT: vor.vv v8, v9, v8 -; FOLDING-NEXT: vor.vv v8, v8, v10 +; FOLDING-NEXT: vsub.vx v10, v10, a0, v0.t +; FOLDING-NEXT: vor.vv v8, v9, v10 +; FOLDING-NEXT: vor.vv v8, v8, v11 ; FOLDING-NEXT: ret %a = load <vscale x 2 x i1>, ptr %x %b = load <vscale x 2 x i1>, ptr %y @@ -444,41 +444,39 @@ define <vscale x 2 x i64> @vwop_vscale_zext_i32i64_multiple_users(ptr %x, ptr %y } define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y, ptr %z) { -; RV32-LABEL: vwop_vscale_zext_i1i32_multiple_users: -; RV32: # %bb.0: -; RV32-NEXT: vsetvli a3, zero, e32, m1, ta, mu -; RV32-NEXT: vlm.v v0, (a0) -; RV32-NEXT: vlm.v v8, (a2) -; RV32-NEXT: vlm.v v9, (a1) -; RV32-NEXT: vmv.v.i v10, 0 -; RV32-NEXT: vmerge.vim v11, v10, 1, v0 -; RV32-NEXT: vmv.v.v v0, v8 -; RV32-NEXT: vmerge.vim v8, v10, 1, v0 -; RV32-NEXT: vadd.vv v10, v11, v8 -; RV32-NEXT: vsub.vv v8, v11, v8 -; RV32-NEXT: vmv.v.v v0, v9 -; RV32-NEXT: vor.vv v10, v10, v11, v0.t -; RV32-NEXT: vor.vv v8, v10, v8 -; RV32-NEXT: ret +; NO_FOLDING-LABEL: vwop_vscale_zext_i1i32_multiple_users: +; NO_FOLDING: # %bb.0: +; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu +; NO_FOLDING-NEXT: vlm.v v0, (a0) +; NO_FOLDING-NEXT: vlm.v v8, (a2) +; NO_FOLDING-NEXT: vlm.v v9, (a1) +; NO_FOLDING-NEXT: vmv.v.i v10, 0 +; NO_FOLDING-NEXT: vmerge.vim v11, v10, 1, v0 +; NO_FOLDING-NEXT: vmv.v.v v0, v8 +; NO_FOLDING-NEXT: vmerge.vim v8, v10, 1, v0 +; NO_FOLDING-NEXT: vadd.vv v10, v11, v8 +; NO_FOLDING-NEXT: vsub.vv v8, v11, v8 +; NO_FOLDING-NEXT: vmv.v.v v0, v9 +; NO_FOLDING-NEXT: vor.vv v10, v10, v11, v0.t +; NO_FOLDING-NEXT: vor.vv v8, v10, v8 +; NO_FOLDING-NEXT: ret ; -; RV64-LABEL: vwop_vscale_zext_i1i32_multiple_users: -; RV64: # %bb.0: -; RV64-NEXT: vsetvli a3, zero, e32, m1, ta, ma -; RV64-NEXT: vlm.v v0, (a0) -; RV64-NEXT: vlm.v v8, (a1) -; RV64-NEXT: vlm.v v9, (a2) -; RV64-NEXT: vmv.v.i v10, 0 -; RV64-NEXT: vmerge.vim v11, v10, 1, v0 -; RV64-NEXT: vmv.v.v v0, v8 -; RV64-NEXT: vmerge.vim v8, v10, 1, v0 -; RV64-NEXT: vmv.v.v v0, v9 -; RV64-NEXT: vmerge.vim v9, v10, 1, v0 -; RV64-NEXT: vmul.vv v8, v11, v8 -; RV64-NEXT: vadd.vv v10, v11, v9 -; RV64-NEXT: vsub.vv v9, v11, v9 -; RV64-NEXT: vor.vv v8, v8, v10 -; RV64-NEXT: vor.vv v8, v8, v9 -; RV64-NEXT: ret +; FOLDING-LABEL: vwop_vscale_zext_i1i32_multiple_users: +; FOLDING: # %bb.0: +; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu +; FOLDING-NEXT: vlm.v v0, (a0) +; FOLDING-NEXT: vlm.v v8, (a2) +; FOLDING-NEXT: vlm.v v9, (a1) +; FOLDING-NEXT: vmv.v.i v10, 0 +; FOLDING-NEXT: vmerge.vim v11, v10, 1, v0 +; FOLDING-NEXT: vmv.v.v v0, v8 +; FOLDING-NEXT: vmerge.vim v8, v10, 1, v0 +; FOLDING-NEXT: vadd.vv v10, v11, v8 +; FOLDING-NEXT: vsub.vv v8, v11, v8 +; FOLDING-NEXT: vmv.v.v v0, v9 +; FOLDING-NEXT: vor.vv v10, v10, v11, v0.t +; FOLDING-NEXT: vor.vv v8, v10, v8 +; FOLDING-NEXT: ret %a = load <vscale x 2 x i1>, ptr %x %b = load <vscale x 2 x i1>, ptr %y %b2 = load <vscale x 2 x i1>, ptr %z @@ -496,40 +494,36 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y, define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, ptr %z) { ; NO_FOLDING-LABEL: vwop_vscale_zext_i1i8_multiple_users: ; NO_FOLDING: # %bb.0: -; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, ma +; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu ; NO_FOLDING-NEXT: vlm.v v0, (a0) -; NO_FOLDING-NEXT: vlm.v v8, (a1) -; NO_FOLDING-NEXT: vlm.v v9, (a2) +; NO_FOLDING-NEXT: vlm.v v8, (a2) +; NO_FOLDING-NEXT: vlm.v v9, (a1) ; NO_FOLDING-NEXT: vmv.v.i v10, 0 ; NO_FOLDING-NEXT: vmerge.vim v11, v10, 1, v0 ; NO_FOLDING-NEXT: vmv1r.v v0, v8 ; NO_FOLDING-NEXT: vmerge.vim v8, v10, 1, v0 +; NO_FOLDING-NEXT: vadd.vv v10, v11, v8 +; NO_FOLDING-NEXT: vsub.vv v8, v11, v8 ; NO_FOLDING-NEXT: vmv1r.v v0, v9 -; NO_FOLDING-NEXT: vmerge.vim v9, v10, 1, v0 -; NO_FOLDING-NEXT: vmul.vv v8, v11, v8 -; NO_FOLDING-NEXT: vadd.vv v10, v11, v9 -; NO_FOLDING-NEXT: vsub.vv v9, v11, v9 -; NO_FOLDING-NEXT: vor.vv v8, v8, v10 -; NO_FOLDING-NEXT: vor.vv v8, v8, v9 +; NO_FOLDING-NEXT: vor.vv v10, v10, v11, v0.t +; NO_FOLDING-NEXT: vor.vv v8, v10, v8 ; NO_FOLDING-NEXT: ret ; ; FOLDING-LABEL: vwop_vscale_zext_i1i8_multiple_users: ; FOLDING: # %bb.0: -; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, ma +; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu ; FOLDING-NEXT: vlm.v v0, (a0) -; FOLDING-NEXT: vlm.v v8, (a1) -; FOLDING-NEXT: vlm.v v9, (a2) +; FOLDING-NEXT: vlm.v v8, (a2) +; FOLDING-NEXT: vlm.v v9, (a1) ; FOLDING-NEXT: vmv.v.i v10, 0 ; FOLDING-NEXT: vmerge.vim v11, v10, 1, v0 ; FOLDING-NEXT: vmv1r.v v0, v8 ; FOLDING-NEXT: vmerge.vim v8, v10, 1, v0 +; FOLDING-NEXT: vadd.vv v10, v11, v8 +; FOLDING-NEXT: vsub.vv v8, v11, v8 ; FOLDING-NEXT: vmv1r.v v0, v9 -; FOLDING-NEXT: vmerge.vim v9, v10, 1, v0 -; FOLDING-NEXT: vmul.vv v8, v11, v8 -; FOLDING-NEXT: vadd.vv v10, v11, v9 -; FOLDING-NEXT: vsub.vv v9, v11, v9 -; FOLDING-NEXT: vor.vv v8, v8, v10 -; FOLDING-NEXT: vor.vv v8, v8, v9 +; FOLDING-NEXT: vor.vv v10, v10, v11, v0.t +; FOLDING-NEXT: vor.vv v8, v10, v8 ; FOLDING-NEXT: ret %a = load <vscale x 2 x i1>, ptr %x %b = load <vscale x 2 x i1>, ptr %y @@ -594,3 +588,6 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i8i32_multiple_users(ptr %x, ptr %y, +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; RV32: {{.*}} +; RV64: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll index 0d52dd7..0a5e501 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll @@ -825,3 +825,56 @@ define <vscale x 2 x i1> @select_cond_x_cond(<vscale x 2 x i1> %x, <vscale x 2 x %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %x, i32 %evl) ret <vscale x 2 x i1> %a } + +define <vscale x 2 x i1> @select_undef_T_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) { +; CHECK-LABEL: select_undef_T_F: +; CHECK: # %bb.0: +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: ret + %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> poison, <vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 %evl) + ret <vscale x 2 x i1> %a +} + +define <vscale x 2 x i1> @select_undef_undef_F(<vscale x 2 x i1> %x, i32 zeroext %evl) { +; CHECK-LABEL: select_undef_undef_F: +; CHECK: # %bb.0: +; CHECK-NEXT: ret + %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> poison, <vscale x 2 x i1> undef, <vscale x 2 x i1> %x, i32 %evl) + ret <vscale x 2 x i1> %a +} + +define <vscale x 2 x i1> @select_unknown_undef_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) { +; CHECK-LABEL: select_unknown_undef_F: +; CHECK: # %bb.0: +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: ret + %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> undef, <vscale x 2 x i1> %y, i32 %evl) + ret <vscale x 2 x i1> %a +} + +define <vscale x 2 x i1> @select_unknown_T_undef(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) { +; CHECK-LABEL: select_unknown_T_undef: +; CHECK: # %bb.0: +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: ret + %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> poison, i32 %evl) + ret <vscale x 2 x i1> %a +} + +define <vscale x 2 x i1> @select_false_T_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %z, i32 zeroext %evl) { +; CHECK-LABEL: select_false_T_F: +; CHECK: # %bb.0: +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: ret + %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %y, <vscale x 2 x i1> %z, i32 %evl) + ret <vscale x 2 x i1> %a +} + +define <vscale x 2 x i1> @select_unknown_T_T(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) { +; CHECK-LABEL: select_unknown_T_T: +; CHECK: # %bb.0: +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: ret + %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %y, i32 %evl) + ret <vscale x 2 x i1> %a +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll index 770bb56..082de2e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll @@ -627,3 +627,259 @@ define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a) { %z = shl <vscale x 8 x i16> %x, splat (i16 2) ret <vscale x 8 x i16> %z } + +; ============================================================================== +; i8 -> i64 +; ============================================================================== + +define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) { +; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsext.vf8 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = sext <vscale x 2 x i8> %b to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) { +; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vzext.vf8 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64_nxv2i8(<vscale x 2 x i8> %a, i64 %b) { +; CHECK-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsll.vx v8, v10, a0 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 + %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %splat + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i32 %b) { +; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsext.vf2 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 +; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 + %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i32 %b) { +; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vzext.vf2 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 +; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 + %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i16 %b) { +; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsext.vf4 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 +; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vsext.vf4 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 + %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i16 %b) { +; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vzext.vf4 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 +; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 + %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i8 %b) { +; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsext.vf8 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 +; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 + %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i8 %b) { +; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-NEXT: vmv.v.x v9, a0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vzext.vf8 v12, v9 +; CHECK-NEXT: vsll.vv v8, v10, v12 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 +; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9 +; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: ret + %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 + %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, %y + ret <vscale x 2 x i64> %z +} + +define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) { +; CHECK-LABEL: vwsll_vi_nxv2i64_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsll.vi v8, v10, 2 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2 +; CHECK-ZVBB-NEXT: ret + %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64> + %z = shl <vscale x 2 x i64> %x, splat (i64 2) + ret <vscale x 2 x i64> %z +} |