diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/binop-zext.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/binop-zext.ll | 40 |
1 files changed, 24 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/binop-zext.ll b/llvm/test/CodeGen/RISCV/rvv/binop-zext.ll index e050240..2d5258f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/binop-zext.ll +++ b/llvm/test/CodeGen/RISCV/rvv/binop-zext.ll @@ -50,10 +50,12 @@ define <vscale x 8 x i32> @mul(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { define <vscale x 8 x i32> @sdiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { ; CHECK-LABEL: sdiv: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-NEXT: vzext.vf4 v12, v8 -; CHECK-NEXT: vzext.vf4 v16, v9 -; CHECK-NEXT: vdivu.vv v8, v12, v16 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v9 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vdivu.vv v12, v12, v10 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32> %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32> @@ -64,10 +66,12 @@ define <vscale x 8 x i32> @sdiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { define <vscale x 8 x i32> @udiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { ; CHECK-LABEL: udiv: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-NEXT: vzext.vf4 v12, v8 -; CHECK-NEXT: vzext.vf4 v16, v9 -; CHECK-NEXT: vdivu.vv v8, v12, v16 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v9 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vdivu.vv v12, v12, v10 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32> %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32> @@ -78,10 +82,12 @@ define <vscale x 8 x i32> @udiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { define <vscale x 8 x i32> @srem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { ; CHECK-LABEL: srem: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-NEXT: vzext.vf4 v12, v8 -; CHECK-NEXT: vzext.vf4 v16, v9 -; CHECK-NEXT: vremu.vv v8, v12, v16 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v9 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vremu.vv v12, v12, v10 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32> %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32> @@ -92,10 +98,12 @@ define <vscale x 8 x i32> @srem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { define <vscale x 8 x i32> @urem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { ; CHECK-LABEL: urem: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma -; CHECK-NEXT: vzext.vf4 v12, v8 -; CHECK-NEXT: vzext.vf4 v16, v9 -; CHECK-NEXT: vremu.vv v8, v12, v16 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v9 +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: vremu.vv v12, v12, v10 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; CHECK-NEXT: vzext.vf2 v8, v12 ; CHECK-NEXT: ret %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32> %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32> |