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Diffstat (limited to 'llvm/test/CodeGen/RISCV/llvm.exp10.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/llvm.exp10.ll212
1 files changed, 106 insertions, 106 deletions
diff --git a/llvm/test/CodeGen/RISCV/llvm.exp10.ll b/llvm/test/CodeGen/RISCV/llvm.exp10.ll
index bfac15e..6fde867 100644
--- a/llvm/test/CodeGen/RISCV/llvm.exp10.ll
+++ b/llvm/test/CodeGen/RISCV/llvm.exp10.ll
@@ -29,9 +29,9 @@ define half @exp10_f16(half %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w a0, fa0
; RV32IFD-NEXT: lui a1, 1048560
; RV32IFD-NEXT: or a0, a0, a1
@@ -46,9 +46,9 @@ define half @exp10_f16(half %x) {
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: .cfi_offset ra, -8
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: lui a1, 1048560
; RV64IFD-NEXT: or a0, a0, a1
@@ -68,9 +68,9 @@ define <1 x half> @exp10_v1f16(<1 x half> %x) {
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: fmv.w.x fa0, a0
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w a0, fa0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
@@ -83,9 +83,9 @@ define <1 x half> @exp10_v1f16(<1 x half> %x) {
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: .cfi_offset ra, -8
; RV64IFD-NEXT: fmv.w.x fa0, a0
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
@@ -107,14 +107,14 @@ define <2 x half> @exp10_v2f16(<2 x half> %x) {
; RV32IFD-NEXT: .cfi_offset fs0, -16
; RV32IFD-NEXT: fmv.w.x fs0, a1
; RV32IFD-NEXT: fmv.w.x fa0, a0
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w s0, fa0
; RV32IFD-NEXT: fmv.s fa0, fs0
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w a1, fa0
; RV32IFD-NEXT: mv a0, s0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -135,14 +135,14 @@ define <2 x half> @exp10_v2f16(<2 x half> %x) {
; RV64IFD-NEXT: .cfi_offset s1, -24
; RV64IFD-NEXT: mv s0, a1
; RV64IFD-NEXT: fmv.w.x fa0, a0
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w s1, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s0
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a1, fa0
; RV64IFD-NEXT: mv a0, s1
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -178,24 +178,24 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) {
; RV32IFD-NEXT: fmv.w.x fs0, a2
; RV32IFD-NEXT: fmv.w.x fs1, a3
; RV32IFD-NEXT: fmv.w.x fa0, a1
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.s fs2, fa0
; RV32IFD-NEXT: fmv.s fa0, fs1
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.x.w a0, fs2
; RV32IFD-NEXT: slli s1, a0, 16
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w a0, fa0
; RV32IFD-NEXT: slli a0, a0, 16
; RV32IFD-NEXT: srli a0, a0, 16
; RV32IFD-NEXT: or s1, a0, s1
; RV32IFD-NEXT: fmv.s fa0, fs0
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w a0, fa0
; RV32IFD-NEXT: sh a0, 4(s0)
; RV32IFD-NEXT: sw s1, 0(s0)
@@ -227,24 +227,24 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) {
; RV64IFD-NEXT: lhu a1, 8(a1)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: fmv.w.x fa0, a1
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs0, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s2
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.x.w a0, fs0
; RV64IFD-NEXT: slli s2, a0, 16
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: slli a0, a0, 48
; RV64IFD-NEXT: srli a0, a0, 48
; RV64IFD-NEXT: or s2, a0, s2
; RV64IFD-NEXT: fmv.w.x fa0, s1
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: sh a0, 4(s0)
; RV64IFD-NEXT: sw s2, 0(s0)
@@ -291,27 +291,27 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) {
; RV32IFD-NEXT: fmv.w.x fs1, a2
; RV32IFD-NEXT: fmv.w.x fs2, a3
; RV32IFD-NEXT: fmv.w.x fa0, a1
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.s fs3, fa0
; RV32IFD-NEXT: fmv.s fa0, fs2
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.s fs2, fa0
; RV32IFD-NEXT: fmv.s fa0, fs1
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.s fs1, fa0
; RV32IFD-NEXT: fmv.s fa0, fs0
-; RV32IFD-NEXT: call __extendhfsf2@plt
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call __extendhfsf2
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.x.w s1, fs1
; RV32IFD-NEXT: fmv.x.w s2, fs2
; RV32IFD-NEXT: fmv.x.w s3, fs3
-; RV32IFD-NEXT: call __truncsfhf2@plt
+; RV32IFD-NEXT: call __truncsfhf2
; RV32IFD-NEXT: fmv.x.w a0, fa0
; RV32IFD-NEXT: sh a0, 6(s0)
; RV32IFD-NEXT: sh s3, 4(s0)
@@ -355,27 +355,27 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) {
; RV64IFD-NEXT: lhu a1, 16(a1)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: fmv.w.x fa0, a1
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs0, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s3
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs1, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s2
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs2, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s1
-; RV64IFD-NEXT: call __extendhfsf2@plt
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call __extendhfsf2
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.x.w s1, fs2
; RV64IFD-NEXT: fmv.x.w s2, fs1
; RV64IFD-NEXT: fmv.x.w s3, fs0
-; RV64IFD-NEXT: call __truncsfhf2@plt
+; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: sh a0, 6(s0)
; RV64IFD-NEXT: sh s3, 4(s0)
@@ -398,7 +398,7 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) {
define float @exp10_f32(float %x) {
; CHECK-LABEL: exp10_f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: tail exp10f@plt
+; CHECK-NEXT: tail exp10f
%r = call float @llvm.exp10.f32(float %x)
ret float %r
}
@@ -410,7 +410,7 @@ define <1 x float> @exp10_v1f32(<1 x float> %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
@@ -421,7 +421,7 @@ define <1 x float> @exp10_v1f32(<1 x float> %x) {
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: .cfi_offset ra, -8
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
@@ -441,10 +441,10 @@ define <2 x float> @exp10_v2f32(<2 x float> %x) {
; RV32IFD-NEXT: .cfi_offset fs0, -16
; RV32IFD-NEXT: .cfi_offset fs1, -24
; RV32IFD-NEXT: fmv.s fs0, fa1
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fs1, fa0
; RV32IFD-NEXT: fmv.s fa0, fs0
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fa1, fa0
; RV32IFD-NEXT: fmv.s fa0, fs1
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@@ -464,10 +464,10 @@ define <2 x float> @exp10_v2f32(<2 x float> %x) {
; RV64IFD-NEXT: .cfi_offset fs0, -16
; RV64IFD-NEXT: .cfi_offset fs1, -24
; RV64IFD-NEXT: fmv.s fs0, fa1
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.s fs1, fa0
; RV64IFD-NEXT: fmv.s fa0, fs0
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.s fa1, fa0
; RV64IFD-NEXT: fmv.s fa0, fs1
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -497,13 +497,13 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) {
; RV32IFD-NEXT: fmv.s fs0, fa2
; RV32IFD-NEXT: fmv.s fs1, fa1
; RV32IFD-NEXT: mv s0, a0
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fs2, fa0
; RV32IFD-NEXT: fmv.s fa0, fs1
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fs1, fa0
; RV32IFD-NEXT: fmv.s fa0, fs0
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fsw fa0, 8(s0)
; RV32IFD-NEXT: fsw fs1, 4(s0)
; RV32IFD-NEXT: fsw fs2, 0(s0)
@@ -533,17 +533,17 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) {
; RV64IFD-NEXT: fmv.s fs1, fa0
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: fmv.s fa0, fa1
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: slli s1, a0, 32
; RV64IFD-NEXT: fmv.s fa0, fs1
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: slli a0, a0, 32
; RV64IFD-NEXT: srli a0, a0, 32
; RV64IFD-NEXT: or s1, a0, s1
; RV64IFD-NEXT: fmv.s fa0, fs0
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fsw fa0, 8(s0)
; RV64IFD-NEXT: sd s1, 0(s0)
; RV64IFD-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
@@ -578,16 +578,16 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) {
; RV32IFD-NEXT: fmv.s fs1, fa2
; RV32IFD-NEXT: fmv.s fs2, fa1
; RV32IFD-NEXT: mv s0, a0
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fs3, fa0
; RV32IFD-NEXT: fmv.s fa0, fs2
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fs2, fa0
; RV32IFD-NEXT: fmv.s fa0, fs1
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fmv.s fs1, fa0
; RV32IFD-NEXT: fmv.s fa0, fs0
-; RV32IFD-NEXT: call exp10f@plt
+; RV32IFD-NEXT: call exp10f
; RV32IFD-NEXT: fsw fa0, 12(s0)
; RV32IFD-NEXT: fsw fs1, 8(s0)
; RV32IFD-NEXT: fsw fs2, 4(s0)
@@ -621,16 +621,16 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) {
; RV64IFD-NEXT: fmv.s fs1, fa2
; RV64IFD-NEXT: fmv.s fs2, fa1
; RV64IFD-NEXT: mv s0, a0
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.s fs3, fa0
; RV64IFD-NEXT: fmv.s fa0, fs2
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.s fs2, fa0
; RV64IFD-NEXT: fmv.s fa0, fs1
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.s fs1, fa0
; RV64IFD-NEXT: fmv.s fa0, fs0
-; RV64IFD-NEXT: call exp10f@plt
+; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fsw fa0, 12(s0)
; RV64IFD-NEXT: fsw fs1, 8(s0)
; RV64IFD-NEXT: fsw fs2, 4(s0)
@@ -650,7 +650,7 @@ define <4 x float> @exp10_v4f32(<4 x float> %x) {
define double @exp10_f64(double %x) {
; CHECK-LABEL: exp10_f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: tail exp10@plt
+; CHECK-NEXT: tail exp10
%r = call double @llvm.exp10.f64(double %x)
ret double %r
}
@@ -673,10 +673,10 @@ define <2 x double> @exp10_v2f64(<2 x double> %x) {
; RV32IFD-NEXT: .cfi_offset fs0, -16
; RV32IFD-NEXT: .cfi_offset fs1, -24
; RV32IFD-NEXT: fmv.d fs0, fa1
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fs1, fa0
; RV32IFD-NEXT: fmv.d fa0, fs0
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fa1, fa0
; RV32IFD-NEXT: fmv.d fa0, fs1
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
@@ -696,10 +696,10 @@ define <2 x double> @exp10_v2f64(<2 x double> %x) {
; RV64IFD-NEXT: .cfi_offset fs0, -16
; RV64IFD-NEXT: .cfi_offset fs1, -24
; RV64IFD-NEXT: fmv.d fs0, fa1
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: fmv.d fa0, fs0
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fa1, fa0
; RV64IFD-NEXT: fmv.d fa0, fs1
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -729,13 +729,13 @@ define <3 x double> @exp10_v3f64(<3 x double> %x) {
; RV32IFD-NEXT: fmv.d fs0, fa2
; RV32IFD-NEXT: fmv.d fs1, fa1
; RV32IFD-NEXT: mv s0, a0
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fs2, fa0
; RV32IFD-NEXT: fmv.d fa0, fs1
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fs1, fa0
; RV32IFD-NEXT: fmv.d fa0, fs0
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fsd fa0, 16(s0)
; RV32IFD-NEXT: fsd fs1, 8(s0)
; RV32IFD-NEXT: fsd fs2, 0(s0)
@@ -764,13 +764,13 @@ define <3 x double> @exp10_v3f64(<3 x double> %x) {
; RV64IFD-NEXT: fmv.d fs0, fa2
; RV64IFD-NEXT: fmv.d fs1, fa1
; RV64IFD-NEXT: mv s0, a0
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fs2, fa0
; RV64IFD-NEXT: fmv.d fa0, fs1
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: fmv.d fa0, fs0
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fsd fa0, 16(s0)
; RV64IFD-NEXT: fsd fs1, 8(s0)
; RV64IFD-NEXT: fsd fs2, 0(s0)
@@ -806,16 +806,16 @@ define <4 x double> @exp10_v4f64(<4 x double> %x) {
; RV32IFD-NEXT: fmv.d fs1, fa2
; RV32IFD-NEXT: fmv.d fs2, fa1
; RV32IFD-NEXT: mv s0, a0
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fs3, fa0
; RV32IFD-NEXT: fmv.d fa0, fs2
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fs2, fa0
; RV32IFD-NEXT: fmv.d fa0, fs1
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fmv.d fs1, fa0
; RV32IFD-NEXT: fmv.d fa0, fs0
-; RV32IFD-NEXT: call exp10@plt
+; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: fsd fa0, 24(s0)
; RV32IFD-NEXT: fsd fs1, 16(s0)
; RV32IFD-NEXT: fsd fs2, 8(s0)
@@ -849,16 +849,16 @@ define <4 x double> @exp10_v4f64(<4 x double> %x) {
; RV64IFD-NEXT: fmv.d fs1, fa2
; RV64IFD-NEXT: fmv.d fs2, fa1
; RV64IFD-NEXT: mv s0, a0
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fs3, fa0
; RV64IFD-NEXT: fmv.d fa0, fs2
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fs2, fa0
; RV64IFD-NEXT: fmv.d fa0, fs1
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: fmv.d fa0, fs0
-; RV64IFD-NEXT: call exp10@plt
+; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: fsd fa0, 24(s0)
; RV64IFD-NEXT: fsd fs1, 16(s0)
; RV64IFD-NEXT: fsd fs2, 8(s0)
generated by cgit v1.1 at 2024-09-07 03:28:25 +0000