diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 6 |
3 files changed, 18 insertions, 26 deletions
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp index 86e4434..ca77a97 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp @@ -110,6 +110,8 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const { switch (RC.getID()) { default: + if (RISCVRI::isVRegClass(RC.TSFlags)) + return getRegBank(RISCV::VRBRegBankID); llvm_unreachable("Register class not supported"); case RISCV::GPRRegClassID: case RISCV::GPRF16RegClassID: @@ -131,20 +133,6 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, case RISCV::FPR64CRegClassID: case RISCV::FPR32CRegClassID: return getRegBank(RISCV::FPRBRegBankID); - case RISCV::VMRegClassID: - case RISCV::VRRegClassID: - case RISCV::VRNoV0RegClassID: - case RISCV::VRM2RegClassID: - case RISCV::VRM2NoV0RegClassID: - case RISCV::VRM4RegClassID: - case RISCV::VRM4NoV0RegClassID: - case RISCV::VMV0RegClassID: - case RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID: - case RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID: - case RISCV::VRM8RegClassID: - case RISCV::VRM8NoV0RegClassID: - case RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID: - return getRegBank(RISCV::VRBRegBankID); } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index ad1821d..686bfd1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -143,22 +143,24 @@ class PseudoToVInst<string PseudoInst> { // This class describes information associated to the LMUL. class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass, - VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx> { + VReg f2regclass, VReg f4regclass, VReg f8regclass, string mx, + VReg moutregclass = VMM1> { bits<3> value = lmul; // This is encoded as the vlmul field of vtype. VReg vrclass = regclass; VReg wvrclass = wregclass; VReg f8vrclass = f8regclass; VReg f4vrclass = f4regclass; VReg f2vrclass = f2regclass; + VReg moutclass = moutregclass; string MX = mx; int octuple = oct; } // Associate LMUL with tablegen records of register classes. def V_M1 : LMULInfo<0b000, 8, VR, VRM2, VR, VR, VR, "M1">; -def V_M2 : LMULInfo<0b001, 16, VRM2, VRM4, VR, VR, VR, "M2">; -def V_M4 : LMULInfo<0b010, 32, VRM4, VRM8, VRM2, VR, VR, "M4">; -def V_M8 : LMULInfo<0b011, 64, VRM8,/*NoVReg*/VR, VRM4, VRM2, VR, "M8">; +def V_M2 : LMULInfo<0b001, 16, VRM2, VRM4, VR, VR, VR, "M2", VMM2>; +def V_M4 : LMULInfo<0b010, 32, VRM4, VRM8, VRM2, VR, VR, "M4", VMM4>; +def V_M8 : LMULInfo<0b011, 64, VRM8,/*NoVReg*/VR, VRM4, VRM2, VR, "M8", VMM8>; def V_MF8 : LMULInfo<0b101, 1, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF8">; def V_MF4 : LMULInfo<0b110, 2, VR, VR, VR,/*NoVReg*/VR,/*NoVReg*/VR, "MF4">; @@ -2668,25 +2670,21 @@ multiclass PseudoVEXT_VF8 { // With LMUL<=1 the source and dest occupy a single register so any overlap // is in the lowest-numbered part. multiclass VPseudoBinaryM_VV<LMULInfo m, int TargetConstraintType = 1> { - defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m, - !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; + defm _VV : VPseudoBinaryM<m.moutclass, m.vrclass, m.vrclass, m, "", TargetConstraintType>; } multiclass VPseudoBinaryM_VX<LMULInfo m, int TargetConstraintType = 1> { defm "_VX" : - VPseudoBinaryM<VR, m.vrclass, GPR, m, - !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; + VPseudoBinaryM<m.moutclass, m.vrclass, GPR, m, "", TargetConstraintType>; } multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> { defm "_V" # f.FX : - VPseudoBinaryM<VR, m.vrclass, f.fprclass, m, - !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; + VPseudoBinaryM<m.moutclass, m.vrclass, f.fprclass, m, "", TargetConstraintType>; } multiclass VPseudoBinaryM_VI<LMULInfo m, int TargetConstraintType = 1> { - defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m, - !if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>; + defm _VI : VPseudoBinaryM<m.moutclass, m.vrclass, simm5, m, "", TargetConstraintType>; } multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 316daf2..1a0533c 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -533,6 +533,12 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs), (add (sequence "V%u", 8, 31), (sequence "V%u", 7, 0)), 1>; +// V0 is likely to be used as mask, so we move it in front of allocation order. +def VMM1 : VReg<VMaskVTs, (add (sequence "V%u", 0, 31)), 1>; +def VMM2 : VReg<VMaskVTs, (add (sequence "V%u", 0, 31, 2)), 1>; +def VMM4 : VReg<VMaskVTs, (add (sequence "V%u", 0, 31, 4)), 1>; +def VMM8 : VReg<VMaskVTs, (add (sequence "V%u", 0, 31, 8)), 1>; + def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>; def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), |