diff options
Diffstat (limited to 'llvm/lib/Target/RISCV')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 281 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 92 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedule.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVScheduleZvk.td | 208 |
9 files changed, 521 insertions, 66 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index f222ba9..d091077 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -24,9 +24,9 @@ def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> { def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVCLMULV", "ReadVCLMULV", "ReadVCLMULV">; def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVCLMULX", "ReadVCLMULV", "ReadVCLMULX">; } class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr, @@ -55,7 +55,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6> def I : RVInstIVI_VROR<funct6, (outs VR:$vd), (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm), opcodestr # ".vi", "$vd, $vs2, $imm$vm">, - SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">; + SchedUnaryMC<"WriteVRotI", "ReadVRotV">; } // op vd, vs2, vs1 @@ -107,10 +107,10 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1, RISCVVFormat opv, string opcodestr> { let RVVConstraint = NoConstraint in def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">; let RVVConstraint = VS2Constraint in def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV">; } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 @@ -142,22 +142,22 @@ let Predicates = [HasStdExtZvkb] in { let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">, - SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", - "ReadVIALUV">; + SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV", + "ReadVGHSHV">; def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkg] let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in { def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">, - SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", - "ReadVIALUV">; + SchedTernaryMC<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV", + "ReadVSHA2CHV">; def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">, - SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", - "ReadVIALUV">; + SchedTernaryMC<"WriteVSHA2CLV", "ReadVSHA2CLV", "ReadVSHA2CLV", + "ReadVSHA2CLV">; def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">, - SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", - "ReadVIALUV">; + SchedTernaryMC<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV", + "ReadVSHA2MSV">; } // Predicates = [HasStdExtZvknhaOrZvknhb] let Predicates = [HasStdExtZvkned] in { @@ -166,26 +166,26 @@ let Predicates = [HasStdExtZvkned] in { defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">; defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">; def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>, - SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">; + SchedUnaryMC<"WriteVAESKF1V", "ReadVAESKF1V">; def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V">; let RVVConstraint = VS2Constraint in def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV">; } // Predicates = [HasStdExtZvkned] let Predicates = [HasStdExtZvksed] in { let RVVConstraint = NoConstraint in def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>, - SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">; + SchedUnaryMC<"WriteVSM4KV", "ReadVSM4KV">; defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">; } // Predicates = [HasStdExtZvksed] let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in { def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>, - SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; + SchedBinaryMC<"WriteVSM3CV", "ReadVSM3CV", "ReadVSM3CV">; def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">, - SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">; + SchedUnaryMC<"WriteVSM3MEV", "ReadVSM3MEV">; } // Predicates = [HasStdExtZvksh] //===----------------------------------------------------------------------===// @@ -280,55 +280,121 @@ multiclass VPseudoBinaryV_S_NoMask_Zvk<LMULInfo m> { def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass>; } -multiclass VPseudoVALU_V_NoMask_Zvk { +multiclass VPseudoVGMUL { foreach m = MxListVF4 in { defvar mx = m.MX; defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx>; + SchedBinary<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV", mx>; } } -multiclass VPseudoVALU_S_NoMask_Zvk { +multiclass VPseudoVAESMV { foreach m = MxListVF4 in { defvar mx = m.MX; + defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>, + SchedBinary<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV", mx>; defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx>; + SchedBinary<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV", mx>; + + } +} + +multiclass VPseudoVSM4R { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>, + SchedBinary<"WriteVSM4RV", "ReadVSM4RV", "ReadVSM4RV", mx>; + defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>, + SchedBinary<"WriteVSM4RV", "ReadVSM4RV", "ReadVSM4RV", mx>; + + } +} + +multiclass VPseudoVGHSH { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>, + SchedTernary<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV", + "ReadVGHSHV", mx>; } } -multiclass VPseudoVALU_V_S_NoMask_Zvk - : VPseudoVALU_V_NoMask_Zvk, VPseudoVALU_S_NoMask_Zvk; +multiclass VPseudoVSHA2CH { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>, + SchedTernary<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV", + "ReadVSHA2CHV", mx>; + } +} + +multiclass VPseudoVSHA2CL { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>, + SchedTernary<"WriteVSHA2CLV", "ReadVSHA2CLV", "ReadVSHA2CLV", + "ReadVSHA2CLV", mx>; + } +} -multiclass VPseudoVALU_VV_NoMask_Zvk { +multiclass VPseudoVSHA2MS { foreach m = MxListVF4 in { defvar mx = m.MX; defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>, - SchedTernary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", "ReadVIALUV", mx>; + SchedTernary<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV", + "ReadVSHA2MSV", mx>; + } +} + +multiclass VPseudoVAESKF1 { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm _VI : VPseudoBinaryNoMaskTU_Zvk<m.vrclass, m.vrclass, uimm5, m>, + SchedBinary<"WriteVAESKF1V", "ReadVAESKF1V", "ReadVAESKF1V", mx, + forceMergeOpRead=true>; + } +} + +multiclass VPseudoVAESKF2 { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm _VI : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, uimm5, m>, + SchedTernary<"WriteVAESKF2V", "ReadVAESKF2V", "ReadVAESKF2V", + "ReadVAESKF2V", mx>; + } +} + +multiclass VPseudoVAESZ { + foreach m = MxListVF4 in { + defvar mx = m.MX; + defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>, + SchedBinary<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV", mx>; } } -multiclass VPseudoVALU_VI_NoMask_Zvk { +multiclass VPseudoVSM3C { foreach m = MxListVF4 in { defvar mx = m.MX; defm _VI : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, uimm5, m>, - SchedTernary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", "ReadVIALUV", mx>; + SchedTernary<"WriteVSM3CV", "ReadVSM3CV", "ReadVSM3CV", + "ReadVSM3CV", mx>; } } -multiclass VPseudoVALU_VI_NoMaskTU_Zvk { +multiclass VPseudoVSM4K { foreach m = MxListVF4 in { defvar mx = m.MX; defm _VI : VPseudoBinaryNoMaskTU_Zvk<m.vrclass, m.vrclass, uimm5, m>, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx, + SchedBinary<"WriteVSM4KV", "ReadVSM4KV", "ReadVSM4KV", mx, forceMergeOpRead=true>; } } -multiclass VPseudoVALU_VV_NoMaskTU_Zvk { +multiclass VPseudoVSM3ME { foreach m = MxListVF4 in { defvar mx = m.MX; defm _VV : VPseudoBinaryNoMaskTU_Zvk<m.vrclass, m.vrclass, m.vrclass, m>, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx, + SchedBinary<"WriteVSM3MEV", "ReadVSM3MEV", "ReadVSM3MEV", mx, forceMergeOpRead=true>; } } @@ -337,10 +403,10 @@ multiclass VPseudoVCLMUL_VV_VX { foreach m = MxList in { defvar mx = m.MX; defm "" : VPseudoBinaryV_VV<m>, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx, + SchedBinary<"WriteVCLMULV", "ReadVCLMULV", "ReadVCLMULV", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX<m>, - SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx, + SchedBinary<"WriteVCLMULX", "ReadVCLMULV", "ReadVCLMULX", mx, forceMergeOpRead=true>; } } @@ -354,28 +420,111 @@ multiclass VPseudoUnaryV_V<LMULInfo m> { } } -multiclass VPseudoVALU_V { +multiclass VPseudoVBREV { foreach m = MxList in { defvar mx = m.MX; defm "" : VPseudoUnaryV_V<m>, - SchedUnary<"WriteVIALUV", "ReadVIALUV", mx, - forceMergeOpRead=true>; + SchedUnary<"WriteVBREVV", "ReadVBREVV", mx, forceMergeOpRead=true>; } } -multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX { +multiclass VPseudoVCLZ { + foreach m = MxList in { + defvar mx = m.MX; + defm "" : VPseudoUnaryV_V<m>, + SchedUnary<"WriteVCLZV", "ReadVCLZV", mx, forceMergeOpRead=true>; + } +} + +multiclass VPseudoVCTZ { + foreach m = MxList in { + defvar mx = m.MX; + defm "" : VPseudoUnaryV_V<m>, + SchedUnary<"WriteVCTZV", "ReadVCTZV", mx, forceMergeOpRead=true>; + } +} + +multiclass VPseudoVCPOP { + foreach m = MxList in { + defvar mx = m.MX; + defm "" : VPseudoUnaryV_V<m>, + SchedUnary<"WriteVCPOPV", "ReadVCPOPV", mx, forceMergeOpRead=true>; + } +} + +multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> { foreach m = MxListW in { + defvar mx = m.MX; + defm "" : VPseudoBinaryW_VV<m>, + SchedBinary<"WriteVWSLLV", "ReadVWSLLV", "ReadVWSLLV", mx, + forceMergeOpRead=true>; + defm "" : VPseudoBinaryW_VX<m>, + SchedBinary<"WriteVWSLLX", "ReadVWSLLV", "ReadVWSLLX", mx, + forceMergeOpRead=true>; defm "" : VPseudoBinaryW_VI<ImmType, m>, - SchedUnary<"WriteVIWALUV", "ReadVIWALUV", m.MX, + SchedUnary<"WriteVWSLLI", "ReadVWSLLV", mx, forceMergeOpRead=true>; } } +multiclass VPseudoVANDN { + foreach m = MxList in { + defm "" : VPseudoBinaryV_VV<m>, + SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, + forceMergeOpRead=true>; + defm "" : VPseudoBinaryV_VX<m>, + SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, + forceMergeOpRead=true>; + } +} + +multiclass VPseudoVBREV8 { + foreach m = MxList in { + defvar mx = m.MX; + defm "" : VPseudoUnaryV_V<m>, + SchedUnary<"WriteVBREV8V", "ReadVBREV8V", mx, forceMergeOpRead=true>; + } +} + +multiclass VPseudoVREV8 { + foreach m = MxList in { + defvar mx = m.MX; + defm "" : VPseudoUnaryV_V<m>, + SchedUnary<"WriteVREV8V", "ReadVREV8V", mx, forceMergeOpRead=true>; + } +} + +multiclass VPseudoVROL { + foreach m = MxList in { + defm "" : VPseudoBinaryV_VV<m>, + SchedBinary<"WriteVRotV", "ReadVRotV", "ReadVRotV", m.MX, + forceMergeOpRead=true>; + defm "" : VPseudoBinaryV_VX<m>, + SchedBinary<"WriteVRotX", "ReadVRotV", "ReadVRotX", m.MX, + forceMergeOpRead=true>; + } +} + +multiclass VPseudoVROR<Operand ImmType> { + defvar Constraint = ""; + foreach m = MxList in { + defvar mx = m.MX; + defm "" : VPseudoBinaryV_VV<m>, + SchedBinary<"WriteVRotV", "ReadVRotV", "ReadVRotV", mx, + forceMergeOpRead=true>; + defm "" : VPseudoBinaryV_VX<m>, + SchedBinary<"WriteVRotX", "ReadVRotV", "ReadVRotX", mx, + forceMergeOpRead=true>; + defm "" : VPseudoBinaryV_VI<ImmType, m>, + SchedUnary<"WriteVRotI", "ReadVRotV", mx, forceMergeOpRead=true>; + } +} + let Predicates = [HasStdExtZvbb] in { - defm PseudoVBREV : VPseudoVALU_V; - defm PseudoVCLZ : VPseudoVALU_V; - defm PseudoVCTZ : VPseudoVALU_V; - defm PseudoVCPOP : VPseudoVALU_V; + defm PseudoVBREV : VPseudoVBREV; + defm PseudoVCLZ : VPseudoVCLZ; + defm PseudoVCTZ : VPseudoVCTZ; + defm PseudoVCPOP : VPseudoVCPOP; defm PseudoVWSLL : VPseudoVWALU_VV_VX_VI<uimm5>; } // Predicates = [HasStdExtZvbb] @@ -385,42 +534,42 @@ let Predicates = [HasStdExtZvbc] in { } // Predicates = [HasStdExtZvbc] let Predicates = [HasStdExtZvkb] in { - defm PseudoVANDN : VPseudoVALU_VV_VX; - defm PseudoVBREV8 : VPseudoVALU_V; - defm PseudoVREV8 : VPseudoVALU_V; - defm PseudoVROL : VPseudoVALU_VV_VX; - defm PseudoVROR : VPseudoVALU_VV_VX_VI<uimm6>; + defm PseudoVANDN : VPseudoVANDN; + defm PseudoVBREV8 : VPseudoVBREV8; + defm PseudoVREV8 : VPseudoVREV8; + defm PseudoVROL : VPseudoVROL; + defm PseudoVROR : VPseudoVROR<uimm6>; } // Predicates = [HasStdExtZvkb] let Predicates = [HasStdExtZvkg] in { - defm PseudoVGHSH : VPseudoVALU_VV_NoMask_Zvk; - defm PseudoVGMUL : VPseudoVALU_V_NoMask_Zvk; + defm PseudoVGHSH : VPseudoVGHSH; + defm PseudoVGMUL : VPseudoVGMUL; } // Predicates = [HasStdExtZvkg] let Predicates = [HasStdExtZvkned] in { - defm PseudoVAESDF : VPseudoVALU_V_S_NoMask_Zvk; - defm PseudoVAESDM : VPseudoVALU_V_S_NoMask_Zvk; - defm PseudoVAESEF : VPseudoVALU_V_S_NoMask_Zvk; - defm PseudoVAESEM : VPseudoVALU_V_S_NoMask_Zvk; - defm PseudoVAESKF1 : VPseudoVALU_VI_NoMaskTU_Zvk; - defm PseudoVAESKF2 : VPseudoVALU_VI_NoMask_Zvk; - defm PseudoVAESZ : VPseudoVALU_S_NoMask_Zvk; + defm PseudoVAESDF : VPseudoVAESMV; + defm PseudoVAESDM : VPseudoVAESMV; + defm PseudoVAESEF : VPseudoVAESMV; + defm PseudoVAESEM : VPseudoVAESMV; + defm PseudoVAESKF1 : VPseudoVAESKF1; + defm PseudoVAESKF2 : VPseudoVAESKF2; + defm PseudoVAESZ : VPseudoVAESZ; } // Predicates = [HasStdExtZvkned] let Predicates = [HasStdExtZvknhaOrZvknhb] in { - defm PseudoVSHA2CH : VPseudoVALU_VV_NoMask_Zvk; - defm PseudoVSHA2CL : VPseudoVALU_VV_NoMask_Zvk; - defm PseudoVSHA2MS : VPseudoVALU_VV_NoMask_Zvk; + defm PseudoVSHA2CH : VPseudoVSHA2CH; + defm PseudoVSHA2CL : VPseudoVSHA2CL; + defm PseudoVSHA2MS : VPseudoVSHA2MS; } // Predicates = [HasStdExtZvknhaOrZvknhb] let Predicates = [HasStdExtZvksed] in { - defm PseudoVSM4K : VPseudoVALU_VI_NoMaskTU_Zvk; - defm PseudoVSM4R : VPseudoVALU_V_S_NoMask_Zvk; + defm PseudoVSM4K : VPseudoVSM4K; + defm PseudoVSM4R : VPseudoVSM4R; } // Predicates = [HasStdExtZvksed] let Predicates = [HasStdExtZvksh] in { - defm PseudoVSM3C : VPseudoVALU_VI_NoMask_Zvk; - defm PseudoVSM3ME : VPseudoVALU_VV_NoMaskTU_Zvk; + defm PseudoVSM3C : VPseudoVSM3C; + defm PseudoVSM3ME : VPseudoVSM3ME; } // Predicates = [HasStdExtZvksh] //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index 65494e7..9ddc428 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -262,4 +262,5 @@ defm : UnsupportedSchedZfa; defm : UnsupportedSchedZfh; defm : UnsupportedSchedSFB; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index a532066..e67da83 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -1298,4 +1298,5 @@ defm : UnsupportedSchedZbc; defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkx; defm : UnsupportedSchedZfa; +defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td index fccdd7e..a379588 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td @@ -367,4 +367,5 @@ defm : UnsupportedSchedSFB; defm : UnsupportedSchedZfa; defm : UnsupportedSchedV; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td index 6e4fb19..6ba2993 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td @@ -748,6 +748,62 @@ foreach mx = SchedMxList in { } } +// Vector Crypto +foreach mx = SchedMxList in { + defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c; + defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c; + // Zvbb + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvbc + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvkb + // VANDN uses WriteVIALU[V|X|I] + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvkg + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // ZvknhaOrZvknhb + let Latency = 3, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvkned + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + let Latency = 1, ReleaseAtCycles = [LMulLat] in + defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP600VectorArith], mx, IsWorstCase>; + // Zvksed + let Latency = 3, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + } +} + // Others def : WriteRes<WriteCSR, [SiFiveP600SYS]>; def : WriteRes<WriteNop, []>; @@ -1032,6 +1088,42 @@ foreach mx = SchedMxList in { def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>; } +// Vector Crypto Extensions +// Zvbb +defm "" : LMULReadAdvance<"ReadVBREVV", 0>; +defm "" : LMULReadAdvance<"ReadVCLZV", 0>; +defm "" : LMULReadAdvance<"ReadVCPOPV", 0>; +defm "" : LMULReadAdvance<"ReadVCTZV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLX", 0>; +// Zvbc +defm "" : LMULReadAdvance<"ReadVCLMULV", 0>; +defm "" : LMULReadAdvance<"ReadVCLMULX", 0>; +// Zvkb +// VANDN uses ReadVIALU[V|X|I] +defm "" : LMULReadAdvance<"ReadVBREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVRotV", 0>; +defm "" : LMULReadAdvance<"ReadVRotX", 0>; +// Zvkg +defm "" : LMULReadAdvance<"ReadVGHSHV", 0>; +defm "" : LMULReadAdvance<"ReadVGMULV", 0>; +// Zvknha or Zvknhb +defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; +// Zvkned +defm "" : LMULReadAdvance<"ReadVAESMVV", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>; +defm "" : LMULReadAdvance<"ReadVAESZV", 0>; +// Zvksed +defm "" : LMULReadAdvance<"ReadVSM4KV", 0>; +defm "" : LMULReadAdvance<"ReadVSM4RV", 0>; +// Zbksh +defm "" : LMULReadAdvance<"ReadVSM3CV", 0>; +defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; + //===----------------------------------------------------------------------===// // Unsupported extensions defm : UnsupportedSchedZabha; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td index 0885e32..31112d1 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td @@ -213,4 +213,5 @@ defm : UnsupportedSchedZbkx; defm : UnsupportedSchedZfa; defm : UnsupportedSchedZfh; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td index e0f1fab..dcd1a93 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td +++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td @@ -312,4 +312,5 @@ defm : UnsupportedSchedZfh; defm : UnsupportedSchedSFB; defm : UnsupportedSchedZabha; defm : UnsupportedSchedXsfvcp; +defm : UnsupportedSchedZvk; } diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td index 0086557..d9a2e38 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedule.td +++ b/llvm/lib/Target/RISCV/RISCVSchedule.td @@ -297,3 +297,4 @@ def : ReadAdvance<ReadAtomicHD, 0>; include "RISCVScheduleZb.td" include "RISCVScheduleV.td" include "RISCVScheduleXSf.td" +include "RISCVScheduleZvk.td" diff --git a/llvm/lib/Target/RISCV/RISCVScheduleZvk.td b/llvm/lib/Target/RISCV/RISCVScheduleZvk.td new file mode 100644 index 0000000..640c456 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVScheduleZvk.td @@ -0,0 +1,208 @@ +//=== RISCVScheduleZvk.td - RISC-V Scheduling Definitions Zvk -*- tablegen ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +/// Define scheduler resources associated with def operands. + +/// Zvbb extension +defm "" : LMULSchedWrites<"WriteVBREVV">; +defm "" : LMULSchedWrites<"WriteVCLZV">; +defm "" : LMULSchedWrites<"WriteVCPOPV">; +defm "" : LMULSchedWrites<"WriteVCTZV">; +defm "" : LMULSchedWrites<"WriteVWSLLV">; +defm "" : LMULSchedWrites<"WriteVWSLLX">; +defm "" : LMULSchedWrites<"WriteVWSLLI">; + +/// Zvbc extension +defm "" : LMULSchedWrites<"WriteVCLMULV">; +defm "" : LMULSchedWrites<"WriteVCLMULX">; + +/// Zvkb extension +// VANDN uses WriteVIALU[V|X|I] +defm "" : LMULSchedWrites<"WriteVBREV8V">; +defm "" : LMULSchedWrites<"WriteVREV8V">; +defm "" : LMULSchedWrites<"WriteVRotV">; +defm "" : LMULSchedWrites<"WriteVRotX">; +defm "" : LMULSchedWrites<"WriteVRotI">; + +/// Zvkg extension +defm "" : LMULSchedWrites<"WriteVGHSHV">; +defm "" : LMULSchedWrites<"WriteVGMULV">; + +/// Zvknha or Zvknhb extensions +defm "" : LMULSchedWrites<"WriteVSHA2CHV">; +defm "" : LMULSchedWrites<"WriteVSHA2CLV">; +defm "" : LMULSchedWrites<"WriteVSHA2MSV">; + +/// Zvkned extension +defm "" : LMULSchedWrites<"WriteVAESMVV">; +defm "" : LMULSchedWrites<"WriteVAESKF1V">; +defm "" : LMULSchedWrites<"WriteVAESKF2V">; +defm "" : LMULSchedWrites<"WriteVAESZV">; + +/// Zvksed extension +defm "" : LMULSchedWrites<"WriteVSM4KV">; +defm "" : LMULSchedWrites<"WriteVSM4RV">; + +/// Zvksh extension +defm "" : LMULSchedWrites<"WriteVSM3CV">; +defm "" : LMULSchedWrites<"WriteVSM3MEV">; + +/// Define scheduler resources associated with use operands. +/// Zvbb extension +defm "" : LMULSchedReads<"ReadVBREVV">; +defm "" : LMULSchedReads<"ReadVCLZV">; +defm "" : LMULSchedReads<"ReadVCPOPV">; +defm "" : LMULSchedReads<"ReadVCTZV">; +defm "" : LMULSchedReads<"ReadVWSLLV">; +defm "" : LMULSchedReads<"ReadVWSLLX">; + +/// Zvbc extension +defm "" : LMULSchedReads<"ReadVCLMULV">; +defm "" : LMULSchedReads<"ReadVCLMULX">; + +/// Zvkb extension +// VANDN uses ReadVIALU[V|X|I] +defm "" : LMULSchedReads<"ReadVBREV8V">; +defm "" : LMULSchedReads<"ReadVREV8V">; +defm "" : LMULSchedReads<"ReadVRotV">; +defm "" : LMULSchedReads<"ReadVRotX">; + +/// Zvkg extension +defm "" : LMULSchedReads<"ReadVGHSHV">; +defm "" : LMULSchedReads<"ReadVGMULV">; + +/// Zvknha or Zvknhb extensions +defm "" : LMULSchedReads<"ReadVSHA2CHV">; +defm "" : LMULSchedReads<"ReadVSHA2CLV">; +defm "" : LMULSchedReads<"ReadVSHA2MSV">; + +/// Zvkned extension +defm "" : LMULSchedReads<"ReadVAESMVV">; +defm "" : LMULSchedReads<"ReadVAESKF1V">; +defm "" : LMULSchedReads<"ReadVAESKF2V">; +defm "" : LMULSchedReads<"ReadVAESZV">; + +/// Zvksed extension +defm "" : LMULSchedReads<"ReadVSM4KV">; +defm "" : LMULSchedReads<"ReadVSM4RV">; + +/// Zvksh extension +defm "" : LMULSchedReads<"ReadVSM3CV">; +defm "" : LMULSchedReads<"ReadVSM3MEV">; + +multiclass UnsupportedSchedZvbb { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVBREVV", []>; +defm "" : LMULWriteRes<"WriteVCLZV", []>; +defm "" : LMULWriteRes<"WriteVCPOPV", []>; +defm "" : LMULWriteRes<"WriteVCTZV", []>; +defm "" : LMULWriteRes<"WriteVWSLLV", []>; +defm "" : LMULWriteRes<"WriteVWSLLX", []>; +defm "" : LMULWriteRes<"WriteVWSLLI", []>; + +defm "" : LMULReadAdvance<"ReadVBREVV", 0>; +defm "" : LMULReadAdvance<"ReadVCLZV", 0>; +defm "" : LMULReadAdvance<"ReadVCPOPV", 0>; +defm "" : LMULReadAdvance<"ReadVCTZV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLX", 0>; +} +} + +multiclass UnsupportedSchedZvbc { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVCLMULV", []>; +defm "" : LMULWriteRes<"WriteVCLMULX", []>; + +defm "" : LMULReadAdvance<"ReadVCLMULV", 0>; +defm "" : LMULReadAdvance<"ReadVCLMULX", 0>; +} +} + +multiclass UnsupportedSchedZvkb { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVBREV8V", []>; +defm "" : LMULWriteRes<"WriteVREV8V", []>; +defm "" : LMULWriteRes<"WriteVRotV", []>; +defm "" : LMULWriteRes<"WriteVRotX", []>; +defm "" : LMULWriteRes<"WriteVRotI", []>; + +defm "" : LMULReadAdvance<"ReadVBREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVRotV", 0>; +defm "" : LMULReadAdvance<"ReadVRotX", 0>; +} +} + +multiclass UnsupportedSchedZvkg { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVGHSHV", []>; +defm "" : LMULWriteRes<"WriteVGMULV", []>; + +defm "" : LMULReadAdvance<"ReadVGHSHV", 0>; +defm "" : LMULReadAdvance<"ReadVGMULV", 0>; +} +} + +multiclass UnsupportedSchedZvknhaOrZvknhb { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVSHA2CHV", []>; +defm "" : LMULWriteRes<"WriteVSHA2CLV", []>; +defm "" : LMULWriteRes<"WriteVSHA2MSV", []>; + +defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; +} +} + +multiclass UnsupportedSchedZvkned { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVAESMVV", []>; +defm "" : LMULWriteRes<"WriteVAESKF1V", []>; +defm "" : LMULWriteRes<"WriteVAESKF2V", []>; +defm "" : LMULWriteRes<"WriteVAESZV", []>; + +defm "" : LMULReadAdvance<"ReadVAESMVV", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>; +defm "" : LMULReadAdvance<"ReadVAESZV", 0>; +} +} + +multiclass UnsupportedSchedZvksed { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVSM4KV", []>; +defm "" : LMULWriteRes<"WriteVSM4RV", []>; + +defm "" : LMULReadAdvance<"ReadVSM4KV", 0>; +defm "" : LMULReadAdvance<"ReadVSM4RV", 0>; +} +} + +multiclass UnsupportedSchedZvksh { +let Unsupported = true in { +defm "" : LMULWriteRes<"WriteVSM3CV", []>; +defm "" : LMULWriteRes<"WriteVSM3MEV", []>; + +defm "" : LMULReadAdvance<"ReadVSM3CV", 0>; +defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; +} +} + +// Helper class to define all RISC-V Vector Crypto extensions as unsupported +multiclass UnsupportedSchedZvk { +defm "" : UnsupportedSchedZvbb; +defm "" : UnsupportedSchedZvbc; +defm "" : UnsupportedSchedZvkb; +defm "" : UnsupportedSchedZvkg; +defm "" : UnsupportedSchedZvknhaOrZvknhb; +defm "" : UnsupportedSchedZvkned; +defm "" : UnsupportedSchedZvksed; +defm "" : UnsupportedSchedZvksh; +} |