diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td index 6e4fb19..6ba2993 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td @@ -748,6 +748,62 @@ foreach mx = SchedMxList in { } } +// Vector Crypto +foreach mx = SchedMxList in { + defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c; + defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c; + // Zvbb + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvbc + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvkb + // VANDN uses WriteVIALU[V|X|I] + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvkg + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // ZvknhaOrZvknhb + let Latency = 3, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + // Zvkned + let Latency = 2, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP600VectorArith], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP600VectorArith], mx, IsWorstCase>; + } + let Latency = 1, ReleaseAtCycles = [LMulLat] in + defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP600VectorArith], mx, IsWorstCase>; + // Zvksed + let Latency = 3, ReleaseAtCycles = [LMulLat] in { + defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP600VEXQ0], mx, IsWorstCase>; + } +} + // Others def : WriteRes<WriteCSR, [SiFiveP600SYS]>; def : WriteRes<WriteNop, []>; @@ -1032,6 +1088,42 @@ foreach mx = SchedMxList in { def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>; } +// Vector Crypto Extensions +// Zvbb +defm "" : LMULReadAdvance<"ReadVBREVV", 0>; +defm "" : LMULReadAdvance<"ReadVCLZV", 0>; +defm "" : LMULReadAdvance<"ReadVCPOPV", 0>; +defm "" : LMULReadAdvance<"ReadVCTZV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLX", 0>; +// Zvbc +defm "" : LMULReadAdvance<"ReadVCLMULV", 0>; +defm "" : LMULReadAdvance<"ReadVCLMULX", 0>; +// Zvkb +// VANDN uses ReadVIALU[V|X|I] +defm "" : LMULReadAdvance<"ReadVBREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVRotV", 0>; +defm "" : LMULReadAdvance<"ReadVRotX", 0>; +// Zvkg +defm "" : LMULReadAdvance<"ReadVGHSHV", 0>; +defm "" : LMULReadAdvance<"ReadVGMULV", 0>; +// Zvknha or Zvknhb +defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>; +// Zvkned +defm "" : LMULReadAdvance<"ReadVAESMVV", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>; +defm "" : LMULReadAdvance<"ReadVAESZV", 0>; +// Zvksed +defm "" : LMULReadAdvance<"ReadVSM4KV", 0>; +defm "" : LMULReadAdvance<"ReadVSM4RV", 0>; +// Zbksh +defm "" : LMULReadAdvance<"ReadVSM3CV", 0>; +defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; + //===----------------------------------------------------------------------===// // Unsupported extensions defm : UnsupportedSchedZabha; |