diff options
Diffstat (limited to 'flang')
| -rw-r--r-- | flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h | 7 | ||||
| -rw-r--r-- | flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp | 145 | ||||
| -rw-r--r-- | flang/lib/Semantics/check-call.cpp | 3 | ||||
| -rw-r--r-- | flang/module/__ppc_intrinsics.f90 | 150 | ||||
| -rw-r--r-- | flang/test/Lower/PowerPC/ppc-vec-convert.f90 | 2588 | ||||
| -rw-r--r-- | flang/test/Semantics/PowerPC/ppc-vector-intrinsics.f90 | 8 |
6 files changed, 2896 insertions, 5 deletions
diff --git a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h index ea028f1..83079116 100644 --- a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h @@ -25,6 +25,9 @@ enum class VecOp { Cmpgt, Cmple, Cmplt, + Convert, + Ctf, + Cvf, Mul, Sl, Sld, @@ -113,6 +116,10 @@ struct PPCIntrinsicLibrary : IntrinsicLibrary { llvm::ArrayRef<fir::ExtendedValue> args); template <VecOp> + fir::ExtendedValue genVecConvert(mlir::Type resultType, + llvm::ArrayRef<fir::ExtendedValue> args); + + template <VecOp> fir::ExtendedValue genVecAnyCompare(mlir::Type resultType, llvm::ArrayRef<fir::ExtendedValue> args); diff --git a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp index ecf8af3..0c949f9 100644 --- a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp @@ -68,6 +68,21 @@ static constexpr IntrinsicHandler ppcHandlers[]{ &PI::genVecCmp<VecOp::Cmplt>), {{{"arg1", asValue}, {"arg2", asValue}}}, /*isElemental=*/true}, + {"__ppc_vec_convert", + static_cast<IntrinsicLibrary::ExtendedGenerator>( + &PI::genVecConvert<VecOp::Convert>), + {{{"v", asValue}, {"mold", asValue}}}, + /*isElemental=*/false}, + {"__ppc_vec_ctf", + static_cast<IntrinsicLibrary::ExtendedGenerator>( + &PI::genVecConvert<VecOp::Ctf>), + {{{"arg1", asValue}, {"arg2", asValue}}}, + /*isElemental=*/true}, + {"__ppc_vec_cvf", + static_cast<IntrinsicLibrary::ExtendedGenerator>( + &PI::genVecConvert<VecOp::Cvf>), + {{{"arg1", asValue}}}, + /*isElemental=*/true}, {"__ppc_vec_mul", static_cast<IntrinsicLibrary::ExtendedGenerator>( &PI::genVecAddAndMulSubXor<VecOp::Mul>), @@ -681,6 +696,136 @@ PPCIntrinsicLibrary::genVecCmp(mlir::Type resultType, return res; } +static inline mlir::Value swapVectorWordPairs(fir::FirOpBuilder &builder, + mlir::Location loc, + mlir::Value arg) { + auto ty = arg.getType(); + auto context{builder.getContext()}; + auto vtype{mlir::VectorType::get(16, mlir::IntegerType::get(context, 8))}; + + if (ty != vtype) + arg = builder.create<mlir::LLVM::BitcastOp>(loc, vtype, arg).getResult(); + + llvm::SmallVector<int64_t, 16> mask{4, 5, 6, 7, 0, 1, 2, 3, + 12, 13, 14, 15, 8, 9, 10, 11}; + arg = builder.create<mlir::vector::ShuffleOp>(loc, arg, arg, mask); + if (ty != vtype) + arg = builder.create<mlir::LLVM::BitcastOp>(loc, ty, arg); + return arg; +} + +// VEC_CONVERT, VEC_CTF, VEC_CVF +template <VecOp vop> +fir::ExtendedValue +PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, + llvm::ArrayRef<fir::ExtendedValue> args) { + auto context{builder.getContext()}; + auto argBases{getBasesForArgs(args)}; + auto vecTyInfo{getVecTypeFromFir(argBases[0])}; + auto mlirTy{vecTyInfo.toMlirVectorType(context)}; + auto vArg1{builder.createConvert(loc, mlirTy, argBases[0])}; + const auto i32Ty{mlir::IntegerType::get(context, 32)}; + + switch (vop) { + case VecOp::Ctf: { + assert(args.size() == 2); + auto convArg{builder.createConvert(loc, i32Ty, argBases[1])}; + auto eTy{vecTyInfo.eleTy.dyn_cast<mlir::IntegerType>()}; + assert(eTy && "Unsupported vector type"); + const auto isUnsigned{eTy.isUnsignedInteger()}; + const auto width{eTy.getWidth()}; + + if (width == 32) { + auto ftype{(isUnsigned) + ? genFuncType<Ty::RealVector<4>, Ty::UnsignedVector<4>, + Ty::Integer<4>>(context, builder) + : genFuncType<Ty::RealVector<4>, Ty::IntegerVector<4>, + Ty::Integer<4>>(context, builder)}; + const llvm::StringRef fname{(isUnsigned) ? "llvm.ppc.altivec.vcfux" + : "llvm.ppc.altivec.vcfsx"}; + auto funcOp{builder.addNamedFunction(loc, fname, ftype)}; + mlir::Value newArgs[] = {argBases[0], convArg}; + auto callOp{builder.create<fir::CallOp>(loc, funcOp, newArgs)}; + + return callOp.getResult(0); + } else if (width == 64) { + auto fTy{mlir::FloatType::getF64(context)}; + auto ty{mlir::VectorType::get(2, fTy)}; + + // vec_vtf(arg1, arg2) = fmul(1.0 / (1 << arg2), llvm.sitofp(arg1)) + auto convOp{(isUnsigned) + ? builder.create<mlir::LLVM::UIToFPOp>(loc, ty, vArg1) + : builder.create<mlir::LLVM::SIToFPOp>(loc, ty, vArg1)}; + + // construct vector<1./(1<<arg1), 1.0/(1<<arg1)> + auto constInt{ + mlir::dyn_cast<mlir::arith::ConstantOp>(argBases[1].getDefiningOp()) + .getValue() + .dyn_cast_or_null<mlir::IntegerAttr>()}; + assert(constInt && "expected integer constant argument"); + double f{1.0 / (1 << constInt.getInt())}; + llvm::SmallVector<double> vals{f, f}; + auto constOp{builder.create<mlir::arith::ConstantOp>( + loc, ty, builder.getF64VectorAttr(vals))}; + + auto mulOp{builder.create<mlir::LLVM::FMulOp>( + loc, ty, convOp->getResult(0), constOp)}; + + return builder.createConvert(loc, fir::VectorType::get(2, fTy), mulOp); + } + llvm_unreachable("invalid element integer kind"); + } + case VecOp::Convert: { + assert(args.size() == 2); + // resultType has mold type (if scalar) or element type (if array) + auto resTyInfo{getVecTypeFromFirType(resultType)}; + auto moldTy{resTyInfo.toMlirVectorType(context)}; + auto firTy{resTyInfo.toFirVectorType()}; + + // vec_convert(v, mold) = bitcast v to "type of mold" + auto conv{builder.create<mlir::LLVM::BitcastOp>(loc, moldTy, vArg1)}; + + return builder.createConvert(loc, firTy, conv); + } + case VecOp::Cvf: { + assert(args.size() == 1); + + mlir::Value newArgs[]{vArg1}; + if (vecTyInfo.isFloat32()) { + // TODO: Handle element ordering + newArgs[0] = swapVectorWordPairs(builder, loc, newArgs[0]); + + const llvm::StringRef fname{"llvm.ppc.vsx.xvcvspdp"}; + auto ftype{ + genFuncType<Ty::RealVector<8>, Ty::RealVector<4>>(context, builder)}; + auto funcOp{builder.addNamedFunction(loc, fname, ftype)}; + auto callOp{builder.create<fir::CallOp>(loc, funcOp, newArgs)}; + + return callOp.getResult(0); + } else if (vecTyInfo.isFloat64()) { + const llvm::StringRef fname{"llvm.ppc.vsx.xvcvdpsp"}; + auto ftype{ + genFuncType<Ty::RealVector<4>, Ty::RealVector<8>>(context, builder)}; + auto funcOp{builder.addNamedFunction(loc, fname, ftype)}; + newArgs[0] = + builder.create<fir::CallOp>(loc, funcOp, newArgs).getResult(0); + auto fvf32Ty{newArgs[0].getType()}; + auto f32type{mlir::FloatType::getF32(context)}; + auto mvf32Ty{mlir::VectorType::get(4, f32type)}; + newArgs[0] = builder.createConvert(loc, mvf32Ty, newArgs[0]); + + // TODO: Handle element ordering + newArgs[0] = swapVectorWordPairs(builder, loc, newArgs[0]); + + return builder.createConvert(loc, fvf32Ty, newArgs[0]); + } + llvm_unreachable("invalid element integer kind"); + } + default: + llvm_unreachable("Invalid vector operation for generator"); + } +} + // VEC_SL, VEC_SLD, VEC_SLDW, VEC_SLL, VEC_SLO, VEC_SR, VEC_SRL, VEC_SRO template <VecOp vop> fir::ExtendedValue diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index 7999d37..3c7b18e 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -1394,6 +1394,9 @@ bool CheckPPCIntrinsic(const Symbol &generic, const Symbol &specific, if (specific.name().ToString().compare(0, 15, "__ppc_vec_sldw_") == 0) { return CheckArgumentIsConstantExprInRange(actuals, 2, 0, 3, messages); } + if (specific.name().ToString().compare(0, 14, "__ppc_vec_ctf_") == 0) { + return CheckArgumentIsConstantExprInRange(actuals, 1, 0, 31, messages); + } return false; } diff --git a/flang/module/__ppc_intrinsics.f90 b/flang/module/__ppc_intrinsics.f90 index d97444a..17f6180 100644 --- a/flang/module/__ppc_intrinsics.f90 +++ b/flang/module/__ppc_intrinsics.f90 @@ -22,6 +22,17 @@ module __ppc_intrinsics !-------------------- ! Vector intrinsic !-------------------- +!! ================ 1 argument function interface ================ +! vector(r) function f(vector(r)) +#define ELEM_FUNC_VRVR_2(VKIND1, VKIND2) \ + elemental vector(real(VKIND1)) function elem_func_vr##VKIND1##vr##VKIND2(arg1); \ + vector(real(VKIND2)), intent(in) :: arg1; \ + end function ; + + ELEM_FUNC_VRVR_2(4,8) ELEM_FUNC_VRVR_2(8,4) + +#undef ELEM_FUNC_VRVR_2 + !! ================ 2 arguments function interface ================ ! vector(i) function f(vector(i), vector(i)) #define ELEM_FUNC_VIVIVI(VKIND) \ @@ -88,6 +99,56 @@ module __ppc_intrinsics vector(real(VKIND)), intent(in) :: arg1, arg2; \ end function ; +! vector(r) function f(vector(i), i) +#define ELEM_FUNC_VRVII(VKIND) \ + elemental vector(real(VKIND)) function elem_func_vr##VKIND##vi##VKIND##i(arg1, arg2); \ + vector(integer(VKIND)), intent(in) :: arg1; \ + integer(8), intent(in) :: arg2; \ + !dir$ ignore_tkr(k) arg2; \ + end function ; + +! vector(r) function f(vector(u), i) +#define ELEM_FUNC_VRVUI(VKIND) \ + elemental vector(real(VKIND)) function elem_func_vr##VKIND##vu##VKIND##i(arg1, arg2); \ + vector(unsigned(VKIND)), intent(in) :: arg1; \ + integer(8), intent(in) :: arg2; \ + !dir$ ignore_tkr(k) arg2; \ + end function ; + +! The following macros are specific for the vec_convert(v, mold) intrinsics as +! the argument keywords are different from the other vector intrinsics. +! +! vector(i) function f(vector(i), vector(i)) +#define FUNC_VEC_CONVERT_VIVIVI(VKIND) \ + pure vector(integer(VKIND)) function func_vec_convert_vi##VKIND##vi##vi##VKIND(v, mold); \ + vector(integer(8)), intent(in) :: v; \ + !dir$ ignore_tkr(tk) v; \ + vector(integer(VKIND)), intent(in) :: mold; \ + !dir$ ignore_tkr(r) mold; \ + end function ; + +! vector(u) function f(vector(i), vector(u)) +#define FUNC_VEC_CONVERT_VUVIVU(VKIND) \ + pure vector(unsigned(VKIND)) function func_vec_convert_vu##VKIND##vi##vu##VKIND(v, mold); \ + vector(integer(8)), intent(in) :: v; \ + !dir$ ignore_tkr(tk) v; \ + vector(unsigned(VKIND)), intent(in) :: mold; \ + !dir$ ignore_tkr(r) mold; \ + end function ; + +! vector(r) function f(vector(i), vector(r)) +#define FUNC_VEC_CONVERT_VRVIVR(VKIND) \ + pure vector(real(VKIND)) function func_vec_convert_vr##VKIND##vi##vr##VKIND(v, mold); \ + vector(integer(8)), intent(in) :: v; \ + !dir$ ignore_tkr(tk) v; \ + vector(real(VKIND)), intent(in) :: mold; \ + !dir$ ignore_tkr(r) mold; \ + end function ; + + FUNC_VEC_CONVERT_VIVIVI(1) FUNC_VEC_CONVERT_VIVIVI(2) FUNC_VEC_CONVERT_VIVIVI(4) FUNC_VEC_CONVERT_VIVIVI(8) + FUNC_VEC_CONVERT_VUVIVU(1) FUNC_VEC_CONVERT_VUVIVU(2) FUNC_VEC_CONVERT_VUVIVU(4) FUNC_VEC_CONVERT_VUVIVU(8) + FUNC_VEC_CONVERT_VRVIVR(4) FUNC_VEC_CONVERT_VRVIVR(8) + ELEM_FUNC_VIVIVI(1) ELEM_FUNC_VIVIVI(2) ELEM_FUNC_VIVIVI(4) ELEM_FUNC_VIVIVI(8) ELEM_FUNC_VUVIVI(1) ELEM_FUNC_VUVIVI(2) ELEM_FUNC_VUVIVI(4) ELEM_FUNC_VUVIVI(8) ELEM_FUNC_VUVUVU(1) ELEM_FUNC_VUVUVU(2) ELEM_FUNC_VUVUVU(4) ELEM_FUNC_VUVUVU(8) @@ -104,7 +165,14 @@ module __ppc_intrinsics ELEM_FUNC_IVIVI(4,1) ELEM_FUNC_IVIVI(4,2) ELEM_FUNC_IVIVI(4,4) ELEM_FUNC_IVIVI(4,8) ELEM_FUNC_IVUVU(4,1) ELEM_FUNC_IVUVU(4,2) ELEM_FUNC_IVUVU(4,4) ELEM_FUNC_IVUVU(4,8) ELEM_FUNC_IVRVR(4,4) ELEM_FUNC_IVRVR(4,8) - + ELEM_FUNC_VRVII(4) ELEM_FUNC_VRVII(8) + ELEM_FUNC_VRVUI(4) ELEM_FUNC_VRVUI(8) + +#undef FUNC_VEC_CONVERT_VRVIVR +#undef FUNC_VEC_CONVERT_VUVIVU +#undef FUNC_VEC_CONVERT_VIVIVI +#undef ELEM_FUNC_VRVUI +#undef ELEM_FUNC_VRVII #undef ELEM_FUNC_IVIVI #undef ELEM_FUNC_IVUVU #undef ELEM_FUNC_VIVIVU_2 @@ -316,6 +384,24 @@ module __ppc_intrinsics end interface mtfsfi public :: mtfsfi +!------------------------- +! vector function(vector) +!------------------------- +#define VR_VR_2(NAME, VKIND1, VKIND2) __ppc_##NAME##_vr##VKIND1##vr##VKIND2 + +#define VEC_VR_VR_2(NAME, VKIND1, VKIND2) \ + procedure(elem_func_vr##VKIND1##vr##VKIND2) :: VR_VR_2(NAME, VKIND1, VKIND2); + +! vec_cvf + VEC_VR_VR_2(vec_cvf,4,8) VEC_VR_VR_2(vec_cvf,8,4) + interface vec_cvf + procedure :: VR_VR_2(vec_cvf,4,8), VR_VR_2(vec_cvf,8,4) + end interface vec_cvf + public :: vec_cvf + +#undef VEC_VR_VR_2 +#undef VR_VR_2 + !--------------------------------- ! vector function(vector, vector) !--------------------------------- @@ -412,6 +498,36 @@ module __ppc_intrinsics end interface vec_cmplt public :: vec_cmplt +! vec_convert +! Argument 'v' has the `ignore_tkr` directive +#define CONVERT_VI_VI_VI(VKIND) __ppc_vec_convert_vi##VKIND##vi##vi##VKIND +#define CONVERT_VU_VI_VU(VKIND) __ppc_vec_convert_vu##VKIND##vi##vu##VKIND +#define CONVERT_VR_VI_VR(VKIND) __ppc_vec_convert_vr##VKIND##vi##vr##VKIND + +#define VEC_CONVERT_VI_VI_VI(VKIND) \ + procedure(func_vec_convert_vi##VKIND##vi##vi##VKIND) :: CONVERT_VI_VI_VI(VKIND); +#define VEC_CONVERT_VU_VI_VU(VKIND) \ + procedure(func_vec_convert_vu##VKIND##vi##vu##VKIND) :: CONVERT_VU_VI_VU(VKIND); +#define VEC_CONVERT_VR_VI_VR(VKIND) \ + procedure(func_vec_convert_vr##VKIND##vi##vr##VKIND) :: CONVERT_VR_VI_VR(VKIND); + + VEC_CONVERT_VI_VI_VI(1) VEC_CONVERT_VI_VI_VI(2) VEC_CONVERT_VI_VI_VI(4) VEC_CONVERT_VI_VI_VI(8) + VEC_CONVERT_VU_VI_VU(1) VEC_CONVERT_VU_VI_VU(2) VEC_CONVERT_VU_VI_VU(4) VEC_CONVERT_VU_VI_VU(8) + VEC_CONVERT_VR_VI_VR(4) VEC_CONVERT_VR_VI_VR(8) + interface vec_convert + procedure :: CONVERT_VI_VI_VI(1), CONVERT_VI_VI_VI(2), CONVERT_VI_VI_VI(4), CONVERT_VI_VI_VI(8) + procedure :: CONVERT_VU_VI_VU(1), CONVERT_VU_VI_VU(2), CONVERT_VU_VI_VU(4), CONVERT_VU_VI_VU(8) + procedure :: CONVERT_VR_VI_VR(4), CONVERT_VR_VI_VR(8) + end interface vec_convert + public :: vec_convert + +#undef VEC_CONVERT_VR_VI_VR +#undef VEC_CONVERT_VU_VI_VU +#undef VEC_CONVERT_VI_VI_VI +#undef CONVERT_VR_VI_VR +#undef CONVERT_VU_VI_VU +#undef CONVERT_VI_VI_VI + ! vec_max VEC_VI_VI_VI(vec_max,1) VEC_VI_VI_VI(vec_max,2) VEC_VI_VI_VI(vec_max,4) VEC_VI_VI_VI(vec_max,8) VEC_VU_VU_VU(vec_max,1) VEC_VU_VU_VU(vec_max,2) VEC_VU_VU_VU(vec_max,4) VEC_VU_VU_VU(vec_max,8) @@ -552,19 +668,18 @@ module __ppc_intrinsics #undef VEC_VU_VR_VR #undef VEC_VR_VR_VR #undef VEC_VU_VU_VU -#undef VEC_V_VR_VU #undef VEC_VU_VU_VU_2 #undef VEC_VI_VI_VI #undef VEC_VU_VI_VI #undef VEC_VI_VI_VU #undef VEC_VI_VI_VU_2 #undef VU_VR_VR +#undef VR_VR_VU_2 #undef VR_VR_VR #undef VU_VU_VU #undef VU_VU_VU_2 -#undef VI_VI_VU_2 #undef VI_VI_VU -#undef VR_VR_VU_2 +#undef VI_VI_VU_2 #undef VU_VI_VI #undef VI_VI_VI @@ -669,4 +784,31 @@ module __ppc_intrinsics #undef VU_VU_VU_I #undef VI_VI_VI_I +!---------------------------------- +! vector function(vector, integer) +!---------------------------------- +! 'i0' stands for the integer argument being ignored via +! the `ignore_tkr' directive. +#define VR_VI_I(NAME, VKIND) __ppc_##NAME##_vr##VKIND##vi##VKIND##i0 +#define VR_VU_I(NAME, VKIND) __ppc_##NAME##_vr##VKIND##vu##VKIND##i0 + +#define VEC_VR_VI_I(NAME, VKIND) \ + procedure(elem_func_vr##VKIND##vi##VKIND##i) :: VR_VI_I(NAME, VKIND); +#define VEC_VR_VU_I(NAME, VKIND) \ + procedure(elem_func_vr##VKIND##vu##VKIND##i) :: VR_VU_I(NAME, VKIND); + +! vec_ctf + VEC_VR_VI_I(vec_ctf,4) VEC_VR_VI_I(vec_ctf,8) + VEC_VR_VU_I(vec_ctf,4) VEC_VR_VU_I(vec_ctf,8) + interface vec_ctf + procedure :: VR_VI_I(vec_ctf,4), VR_VI_I(vec_ctf,8) + procedure :: VR_VU_I(vec_ctf,4), VR_VU_I(vec_ctf,8) + end interface vec_ctf + public :: vec_ctf + +#undef VEC_VR_VU_I +#undef VEC_VR_VI_I +#undef VR_VU_I +#undef VR_VI_I + end module __ppc_intrinsics diff --git a/flang/test/Lower/PowerPC/ppc-vec-convert.f90 b/flang/test/Lower/PowerPC/ppc-vec-convert.f90 new file mode 100644 index 0000000..587d7fc --- /dev/null +++ b/flang/test/Lower/PowerPC/ppc-vec-convert.f90 @@ -0,0 +1,2588 @@ +! RUN: bbc -emit-fir %s -o - | FileCheck --check-prefixes="CHECK-FIR" %s +! RUN: %flang_fc1 -emit-fir %s -o - | fir-opt --fir-to-llvm-ir | FileCheck --check-prefixes="CHECK-LLVMIR" %s +! RUN: %flang_fc1 -emit-llvm %s -o - | FileCheck --check-prefixes="CHECK" %s +! REQUIRES: target=powerpc{{.*}} + +!--------- +! vec_ctf +!--------- +! CHECK-LABEL: vec_ctf_test_i4i1 +subroutine vec_ctf_test_i4i1(arg1) + vector(integer(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_1) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i8 +! CHECK-FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (i8) -> i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[carg2]]) fastmath<contract> : (!fir.vector<4:i32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i8) : i8 +! CHECK-LLVMIR: %[[carg2:.*]] = llvm.sext %[[arg2]] : i8 to i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[carg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i4i1 + +! CHECK-LABEL: vec_ctf_test_i4i2 +subroutine vec_ctf_test_i4i2(arg1) + vector(integer(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_2) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i16 +! CHECK-FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (i16) -> i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[carg2]]) fastmath<contract> : (!fir.vector<4:i32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i16) : i16 +! CHECK-LLVMIR: %[[carg2:.*]] = llvm.sext %[[arg2]] : i16 to i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[carg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i4i2 + +! CHECK-LABEL: vec_ctf_test_i4i4 +subroutine vec_ctf_test_i4i4(arg1) + vector(integer(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_4) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[arg2]]) fastmath<contract> : (!fir.vector<4:i32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i32) : i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[arg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i4i4 + +! CHECK-LABEL: vec_ctf_test_i4i8 +subroutine vec_ctf_test_i4i8(arg1) + vector(integer(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_8) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i64 +! CHECK-FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (i64) -> i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[carg2]]) fastmath<contract> : (!fir.vector<4:i32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i64) : i64 +! CHECK-LLVMIR: %[[carg2:.*]] = llvm.trunc %[[arg2]] : i64 to i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfsx(%[[arg1]], %[[carg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i4i8 + +! CHECK-LABEL: vec_ctf_test_i8i1 +subroutine vec_ctf_test_i8i1(arg1) + vector(integer(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_1) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.sitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.sitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = sitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i8i1 + +! CHECK-LABEL: vec_ctf_test_i8i2 +subroutine vec_ctf_test_i8i2(arg1) + vector(integer(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_2) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.sitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.sitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = sitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i8i2 + +! CHECK-LABEL: vec_ctf_test_i8i4 +subroutine vec_ctf_test_i8i4(arg1) + vector(integer(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_4) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.sitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.sitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = sitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i8i4 + +! CHECK-LABEL: vec_ctf_test_i8i8 +subroutine vec_ctf_test_i8i8(arg1) + vector(integer(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_8) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.sitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.sitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = sitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_i8i8 + +! CHECK-LABEL: vec_ctf_test_u4i1 +subroutine vec_ctf_test_u4i1(arg1) + vector(unsigned(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_1) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i8 +! CHECK-FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (i8) -> i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[carg2]]) fastmath<contract> : (!fir.vector<4:ui32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i8) : i8 +! CHECK-LLVMIR: %[[carg2:.*]] = llvm.sext %[[arg2]] : i8 to i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[carg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u4i1 + +! CHECK-LABEL: vec_ctf_test_u4i2 +subroutine vec_ctf_test_u4i2(arg1) + vector(unsigned(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_2) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i16 +! CHECK-FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (i16) -> i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[carg2]]) fastmath<contract> : (!fir.vector<4:ui32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i16) : i16 +! CHECK-LLVMIR: %[[carg2:.*]] = llvm.sext %[[arg2]] : i16 to i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[carg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u4i2 + +! CHECK-LABEL: vec_ctf_test_u4i4 +subroutine vec_ctf_test_u4i4(arg1) + vector(unsigned(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_4) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[arg2]]) fastmath<contract> : (!fir.vector<4:ui32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i32) : i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[arg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u4i4 + +! CHECK-LABEL: vec_ctf_test_u4i8 +subroutine vec_ctf_test_u4i8(arg1) + vector(unsigned(4)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_ctf(arg1, 1_8) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[arg2:.*]] = arith.constant 1 : i64 +! CHECK-FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (i64) -> i32 +! CHECK-FIR: %[[r:.*]] = fir.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[carg2]]) fastmath<contract> : (!fir.vector<4:ui32>, i32) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[arg2:.*]] = llvm.mlir.constant(1 : i64) : i64 +! CHECK-LLVMIR: %[[carg2:.*]] = llvm.trunc %[[arg2]] : i64 to i32 +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.altivec.vcfux(%[[arg1]], %[[carg2]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, i32) -> vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = call contract <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32> %[[arg1]], i32 1) +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u4i8 + +! CHECK-LABEL: vec_ctf_test_u8i1 +subroutine vec_ctf_test_u8i1(arg1) + vector(unsigned(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_1) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.uitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.uitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = uitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u8i1 + +! CHECK-LABEL: vec_ctf_test_u8i2 +subroutine vec_ctf_test_u8i2(arg1) + vector(unsigned(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_2) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.uitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.uitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = uitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u8i2 + +! CHECK-LABEL: vec_ctf_test_u8i4 +subroutine vec_ctf_test_u8i4(arg1) + vector(unsigned(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_4) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.uitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.uitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = uitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u8i4 + +! CHECK-LABEL: vec_ctf_test_u8i8 +subroutine vec_ctf_test_u8i8(arg1) + vector(unsigned(8)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_ctf(arg1, 3_8) + +! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[varg:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[carg:.*]] = llvm.uitofp %[[varg]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[cst:.*]] = arith.constant dense<1.250000e-01> : vector<2xf64> +! CHECK-FIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[carg:.*]] = llvm.uitofp %[[arg1]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: %[[cst:.*]] = llvm.mlir.constant(dense<1.250000e-01> : vector<2xf64>) : vector<2xf64> +! CHECK-LLVMIR: %[[r:.*]] = llvm.fmul %[[carg]], %[[cst]] : vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[carg:.*]] = uitofp <2 x i64> %[[arg1]] to <2 x double> +! CHECK: %[[r:.*]] = fmul <2 x double> %[[carg]], <double 1.250000e-01, double 1.250000e-01> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_ctf_test_u8i8 + +!------------- +! vec_convert +!------------- +! CHECK-LABEL: vec_convert_test_i1i1 +subroutine vec_convert_test_i1i1(v, mold) + vector(integer(1)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: store <16 x i8> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1i1 + +! CHECK-LABEL: vec_convert_test_i1i2 +subroutine vec_convert_test_i1i2(v, mold) + vector(integer(1)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1i2 + +! CHECK-LABEL: vec_convert_test_i1i4 +subroutine vec_convert_test_i1i4(v, mold) + vector(integer(1)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1i4 + +! CHECK-LABEL: vec_convert_test_i1i8 +subroutine vec_convert_test_i1i8(v, mold) + vector(integer(1)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1i8 + +! CHECK-LABEL: vec_convert_test_i1u1 +subroutine vec_convert_test_i1u1(v, mold) + vector(integer(1)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: store <16 x i8> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1u1 + +! CHECK-LABEL: vec_convert_test_i1u2 +subroutine vec_convert_test_i1u2(v, mold) + vector(integer(1)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1u2 + +! CHECK-LABEL: vec_convert_test_i1u4 +subroutine vec_convert_test_i1u4(v, mold) + vector(integer(1)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1u4 + +! CHECK-LABEL: vec_convert_test_i1u8 +subroutine vec_convert_test_i1u8(v, mold) + vector(integer(1)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1u8 + +! CHECK-LABEL: vec_convert_test_i1r4 +subroutine vec_convert_test_i1r4(v, mold) + vector(integer(1)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1r4 + +! CHECK-LABEL: vec_convert_test_i1r8 +subroutine vec_convert_test_i1r8(v, mold) + vector(integer(1)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1r8 + +! CHECK-LABEL: vec_convert_test_i2i1 +subroutine vec_convert_test_i2i1(v, mold) + vector(integer(2)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2i1 + +! CHECK-LABEL: vec_convert_test_i2i2 +subroutine vec_convert_test_i2i2(v, mold) + vector(integer(2)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: store <8 x i16> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2i2 + +! CHECK-LABEL: vec_convert_test_i2i4 +subroutine vec_convert_test_i2i4(v, mold) + vector(integer(2)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2i4 + +! CHECK-LABEL: vec_convert_test_i2i8 +subroutine vec_convert_test_i2i8(v, mold) + vector(integer(2)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2i8 + +! CHECK-LABEL: vec_convert_test_i2u1 +subroutine vec_convert_test_i2u1(v, mold) + vector(integer(2)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2u1 + +! CHECK-LABEL: vec_convert_test_i2u2 +subroutine vec_convert_test_i2u2(v, mold) + vector(integer(2)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: store <8 x i16> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2u2 + +! CHECK-LABEL: vec_convert_test_i2u4 +subroutine vec_convert_test_i2u4(v, mold) + vector(integer(2)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2u4 + +! CHECK-LABEL: vec_convert_test_i2u8 +subroutine vec_convert_test_i2u8(v, mold) + vector(integer(2)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2u8 + +! CHECK-LABEL: vec_convert_test_i2r4 +subroutine vec_convert_test_i2r4(v, mold) + vector(integer(2)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2r4 + +! CHECK-LABEL: vec_convert_test_i2r8 +subroutine vec_convert_test_i2r8(v, mold) + vector(integer(2)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:i16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i2r8 + +! CHECK-LABEL: vec_convert_test_i4i1 +subroutine vec_convert_test_i4i1(v, mold) + vector(integer(4)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4i1 + +! CHECK-LABEL: vec_convert_test_i4i2 +subroutine vec_convert_test_i4i2(v, mold) + vector(integer(4)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4i2 + +! CHECK-LABEL: vec_convert_test_i4i4 +subroutine vec_convert_test_i4i4(v, mold) + vector(integer(4)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: store <4 x i32> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4i4 + +! CHECK-LABEL: vec_convert_test_i4i8 +subroutine vec_convert_test_i4i8(v, mold) + vector(integer(4)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4i8 + +! CHECK-LABEL: vec_convert_test_i4u1 +subroutine vec_convert_test_i4u1(v, mold) + vector(integer(4)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4u1 + +! CHECK-LABEL: vec_convert_test_i4u2 +subroutine vec_convert_test_i4u2(v, mold) + vector(integer(4)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4u2 + +! CHECK-LABEL: vec_convert_test_i4u4 +subroutine vec_convert_test_i4u4(v, mold) + vector(integer(4)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: store <4 x i32> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4u4 + +! CHECK-LABEL: vec_convert_test_i4u8 +subroutine vec_convert_test_i4u8(v, mold) + vector(integer(4)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4u8 + +! CHECK-LABEL: vec_convert_test_i4r4 +subroutine vec_convert_test_i4r4(v, mold) + vector(integer(4)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4r4 + +! CHECK-LABEL: vec_convert_test_i4r8 +subroutine vec_convert_test_i4r8(v, mold) + vector(integer(4)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4r8 + +! CHECK-LABEL: vec_convert_test_i8i1 +subroutine vec_convert_test_i8i1(v, mold) + vector(integer(8)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8i1 + +! CHECK-LABEL: vec_convert_test_i8i2 +subroutine vec_convert_test_i8i2(v, mold) + vector(integer(8)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8i2 + +! CHECK-LABEL: vec_convert_test_i8i4 +subroutine vec_convert_test_i8i4(v, mold) + vector(integer(8)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8i4 + +! CHECK-LABEL: vec_convert_test_i8i8 +subroutine vec_convert_test_i8i8(v, mold) + vector(integer(8)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: store <2 x i64> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8i8 + +! CHECK-LABEL: vec_convert_test_i8u1 +subroutine vec_convert_test_i8u1(v, mold) + vector(integer(8)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8u1 + +! CHECK-LABEL: vec_convert_test_i8u2 +subroutine vec_convert_test_i8u2(v, mold) + vector(integer(8)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8u2 + +! CHECK-LABEL: vec_convert_test_i8u4 +subroutine vec_convert_test_i8u4(v, mold) + vector(integer(8)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8u4 + +! CHECK-LABEL: vec_convert_test_i8u8 +subroutine vec_convert_test_i8u8(v, mold) + vector(integer(8)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: store <2 x i64> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8u8 + +! CHECK-LABEL: vec_convert_test_i8r4 +subroutine vec_convert_test_i8r4(v, mold) + vector(integer(8)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8r4 + +! CHECK-LABEL: vec_convert_test_i8r8 +subroutine vec_convert_test_i8r8(v, mold) + vector(integer(8)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:i64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i8r8 + +! CHECK-LABEL: vec_convert_test_u1i1 +subroutine vec_convert_test_u1i1(v, mold) + vector(unsigned(1)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: store <16 x i8> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1i1 + +! CHECK-LABEL: vec_convert_test_u1i2 +subroutine vec_convert_test_u1i2(v, mold) + vector(unsigned(1)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1i2 + +! CHECK-LABEL: vec_convert_test_u1i4 +subroutine vec_convert_test_u1i4(v, mold) + vector(unsigned(1)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1i4 + +! CHECK-LABEL: vec_convert_test_u1i8 +subroutine vec_convert_test_u1i8(v, mold) + vector(unsigned(1)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1i8 + +! CHECK-LABEL: vec_convert_test_u1u1 +subroutine vec_convert_test_u1u1(v, mold) + vector(unsigned(1)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: store <16 x i8> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1u1 + +! CHECK-LABEL: vec_convert_test_u1u2 +subroutine vec_convert_test_u1u2(v, mold) + vector(unsigned(1)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1u2 + +! CHECK-LABEL: vec_convert_test_u1u4 +subroutine vec_convert_test_u1u4(v, mold) + vector(unsigned(1)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1u4 + +! CHECK-LABEL: vec_convert_test_u1u8 +subroutine vec_convert_test_u1u8(v, mold) + vector(unsigned(1)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1u8 + +! CHECK-LABEL: vec_convert_test_u1r4 +subroutine vec_convert_test_u1r4(v, mold) + vector(unsigned(1)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1r4 + +! CHECK-LABEL: vec_convert_test_u1r8 +subroutine vec_convert_test_u1r8(v, mold) + vector(unsigned(1)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<16:ui8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<16xi8> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<16xi8> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u1r8 + +! CHECK-LABEL: vec_convert_test_u2i1 +subroutine vec_convert_test_u2i1(v, mold) + vector(unsigned(2)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2i1 + +! CHECK-LABEL: vec_convert_test_u2i2 +subroutine vec_convert_test_u2i2(v, mold) + vector(unsigned(2)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: store <8 x i16> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2i2 + +! CHECK-LABEL: vec_convert_test_u2i4 +subroutine vec_convert_test_u2i4(v, mold) + vector(unsigned(2)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2i4 + +! CHECK-LABEL: vec_convert_test_u2i8 +subroutine vec_convert_test_u2i8(v, mold) + vector(unsigned(2)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2i8 + +! CHECK-LABEL: vec_convert_test_u2u1 +subroutine vec_convert_test_u2u1(v, mold) + vector(unsigned(2)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2u1 + +! CHECK-LABEL: vec_convert_test_u2u2 +subroutine vec_convert_test_u2u2(v, mold) + vector(unsigned(2)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: store <8 x i16> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2u2 + +! CHECK-LABEL: vec_convert_test_u2u4 +subroutine vec_convert_test_u2u4(v, mold) + vector(unsigned(2)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2u4 + +! CHECK-LABEL: vec_convert_test_u2u8 +subroutine vec_convert_test_u2u8(v, mold) + vector(unsigned(2)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2u8 + +! CHECK-LABEL: vec_convert_test_u2r4 +subroutine vec_convert_test_u2r4(v, mold) + vector(unsigned(2)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2r4 + +! CHECK-LABEL: vec_convert_test_u2r8 +subroutine vec_convert_test_u2r8(v, mold) + vector(unsigned(2)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<8:ui16>) -> vector<8xi16> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<8xi16> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<8xi16> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <8 x i16>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <8 x i16> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u2r8 + +! CHECK-LABEL: vec_convert_test_u4i1 +subroutine vec_convert_test_u4i1(v, mold) + vector(unsigned(4)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4i1 + +! CHECK-LABEL: vec_convert_test_u4i2 +subroutine vec_convert_test_u4i2(v, mold) + vector(unsigned(4)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4i2 + +! CHECK-LABEL: vec_convert_test_u4i4 +subroutine vec_convert_test_u4i4(v, mold) + vector(unsigned(4)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: store <4 x i32> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4i4 + +! CHECK-LABEL: vec_convert_test_u4i8 +subroutine vec_convert_test_u4i8(v, mold) + vector(unsigned(4)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4i8 + +! CHECK-LABEL: vec_convert_test_u4u1 +subroutine vec_convert_test_u4u1(v, mold) + vector(unsigned(4)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4u1 + +! CHECK-LABEL: vec_convert_test_u4u2 +subroutine vec_convert_test_u4u2(v, mold) + vector(unsigned(4)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4u2 + +! CHECK-LABEL: vec_convert_test_u4u4 +subroutine vec_convert_test_u4u4(v, mold) + vector(unsigned(4)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: store <4 x i32> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4u4 + +! CHECK-LABEL: vec_convert_test_u4u8 +subroutine vec_convert_test_u4u8(v, mold) + vector(unsigned(4)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4u8 + +! CHECK-LABEL: vec_convert_test_u4r4 +subroutine vec_convert_test_u4r4(v, mold) + vector(unsigned(4)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4r4 + +! CHECK-LABEL: vec_convert_test_u4r8 +subroutine vec_convert_test_u4r8(v, mold) + vector(unsigned(4)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:ui32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xi32> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u4r8 + +! CHECK-LABEL: vec_convert_test_u8i1 +subroutine vec_convert_test_u8i1(v, mold) + vector(unsigned(8)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8i1 + +! CHECK-LABEL: vec_convert_test_u8i2 +subroutine vec_convert_test_u8i2(v, mold) + vector(unsigned(8)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8i2 + +! CHECK-LABEL: vec_convert_test_u8i4 +subroutine vec_convert_test_u8i4(v, mold) + vector(unsigned(8)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8i4 + +! CHECK-LABEL: vec_convert_test_u8i8 +subroutine vec_convert_test_u8i8(v, mold) + vector(unsigned(8)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: store <2 x i64> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8i8 + +! CHECK-LABEL: vec_convert_test_u8u1 +subroutine vec_convert_test_u8u1(v, mold) + vector(unsigned(8)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8u1 + +! CHECK-LABEL: vec_convert_test_u8u2 +subroutine vec_convert_test_u8u2(v, mold) + vector(unsigned(8)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8u2 + +! CHECK-LABEL: vec_convert_test_u8u4 +subroutine vec_convert_test_u8u4(v, mold) + vector(unsigned(8)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8u4 + +! CHECK-LABEL: vec_convert_test_u8u8 +subroutine vec_convert_test_u8u8(v, mold) + vector(unsigned(8)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: store <2 x i64> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8u8 + +! CHECK-LABEL: vec_convert_test_u8r4 +subroutine vec_convert_test_u8r4(v, mold) + vector(unsigned(8)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8r4 + +! CHECK-LABEL: vec_convert_test_u8r8 +subroutine vec_convert_test_u8r8(v, mold) + vector(unsigned(8)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xi64> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8r8 + +! CHECK-LABEL: vec_convert_test_r4i1 +subroutine vec_convert_test_r4i1(v, mold) + vector(real(4)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4i1 + +! CHECK-LABEL: vec_convert_test_r4i2 +subroutine vec_convert_test_r4i2(v, mold) + vector(real(4)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4i2 + +! CHECK-LABEL: vec_convert_test_r4i4 +subroutine vec_convert_test_r4i4(v, mold) + vector(real(4)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4i4 + +! CHECK-LABEL: vec_convert_test_r4i8 +subroutine vec_convert_test_r4i8(v, mold) + vector(real(4)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4i8 + +! CHECK-LABEL: vec_convert_test_r4u1 +subroutine vec_convert_test_r4u1(v, mold) + vector(real(4)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4u1 + +! CHECK-LABEL: vec_convert_test_r4u2 +subroutine vec_convert_test_r4u2(v, mold) + vector(real(4)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4u2 + +! CHECK-LABEL: vec_convert_test_r4u4 +subroutine vec_convert_test_r4u4(v, mold) + vector(real(4)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4u4 + +! CHECK-LABEL: vec_convert_test_r4u8 +subroutine vec_convert_test_r4u8(v, mold) + vector(real(4)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4u8 + +! CHECK-LABEL: vec_convert_test_r4r4 +subroutine vec_convert_test_r4r4(v, mold) + vector(real(4)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: store <4 x float> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4r4 + +! CHECK-LABEL: vec_convert_test_r4r8 +subroutine vec_convert_test_r4r8(v, mold) + vector(real(4)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<4xf32> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xf32> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <4 x float>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x float> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r4r8 + +! CHECK-LABEL: vec_convert_test_r8i1 +subroutine vec_convert_test_r8i1(v, mold) + vector(real(8)) :: v + vector(integer(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8i1 + +! CHECK-LABEL: vec_convert_test_r8i2 +subroutine vec_convert_test_r8i2(v, mold) + vector(real(8)) :: v + vector(integer(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8i2 + +! CHECK-LABEL: vec_convert_test_r8i4 +subroutine vec_convert_test_r8i4(v, mold) + vector(real(8)) :: v + vector(integer(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:i32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8i4 + +! CHECK-LABEL: vec_convert_test_r8i8 +subroutine vec_convert_test_r8i8(v, mold) + vector(real(8)) :: v + vector(integer(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:i64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:i64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8i8 + +! CHECK-LABEL: vec_convert_test_r8u1 +subroutine vec_convert_test_r8u1(v, mold) + vector(real(8)) :: v + vector(unsigned(1)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:ui8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:ui8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<16xi8> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <16 x i8> +! CHECK: store <16 x i8> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8u1 + +! CHECK-LABEL: vec_convert_test_r8u2 +subroutine vec_convert_test_r8u2(v, mold) + vector(real(8)) :: v + vector(unsigned(2)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:ui16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:ui16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8u2 + +! CHECK-LABEL: vec_convert_test_r8u4 +subroutine vec_convert_test_r8u4(v, mold) + vector(real(8)) :: v + vector(unsigned(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<4xi32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xi32>) -> !fir.vector<4:ui32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:ui32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<4xi32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xi32>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <4 x i32> +! CHECK: store <4 x i32> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8u4 + +! CHECK-LABEL: vec_convert_test_r8u8 +subroutine vec_convert_test_r8u8(v, mold) + vector(real(8)) :: v + vector(unsigned(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<2xi64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xi64>) -> !fir.vector<2:ui64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:ui64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<2xi64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xi64>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <2 x i64> +! CHECK: store <2 x i64> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8u8 + +! CHECK-LABEL: vec_convert_test_r8r4 +subroutine vec_convert_test_r8r4(v, mold) + vector(real(8)) :: v + vector(real(4)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xf64> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x double> %[[v]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8r4 + +! CHECK-LABEL: vec_convert_test_r8r8 +subroutine vec_convert_test_r8r8(v, mold) + vector(real(8)) :: v + vector(real(8)) :: mold, r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[vc:.*]] = fir.convert %[[v]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[vc]] : vector<2xf64> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <2 x double>, ptr %0, align 16 +! CHECK: store <2 x double> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_r8r8 + +! CHECK-LABEL: vec_convert_test_i1i1_array +subroutine vec_convert_test_i1i1_array(v, mold) + vector(integer(1)) :: v + vector(integer(1)) :: mold(4, 8), r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>> +! CHECK-FIR: %[[cv:.*]] = fir.convert %[[v]] : (!fir.vector<16:i8>) -> vector<16xi8> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[cv]] : vector<16xi8> to vector<16xi8> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<16xi8>) -> !fir.vector<16:i8> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<16:i8>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>> +! CHECK-LLVMIR: llvm.store %[[v]], %{{.*}} : !llvm.ptr<vector<16xi8>> + +! CHECK: %[[v:.*]] = load <16 x i8>, ptr %{{.*}}, align 16 +! CHECK: store <16 x i8> %[[v]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i1i1_array + +! CHECK-LABEL: vec_convert_test_i4r8_array +subroutine vec_convert_test_i4r8_array(v, mold) + vector(integer(4)) :: v + vector(real(8)) :: mold(2, 4, 8), r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>> +! CHECK-FIR: %[[cv:.*]] = fir.convert %[[v]] : (!fir.vector<4:i32>) -> vector<4xi32> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[cv]] : vector<4xi32> to vector<2xf64> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<2xf64>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<4xi32> to vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[v:.*]] = load <4 x i32>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = bitcast <4 x i32> %[[v]] to <2 x double> +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_i4r8_array + +! CHECK-LABEL: vec_convert_test_u8i2_array +subroutine vec_convert_test_u8i2_array(v, mold) + vector(unsigned(8)) :: v + vector(integer(2)) :: mold(10), r + r = vec_convert(v, mold) + +! CHECK-FIR: %[[v:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>> +! CHECK-FIR: %[[cv:.*]] = fir.convert %[[v]] : (!fir.vector<2:ui64>) -> vector<2xi64> +! CHECK-FIR: %[[b:.*]] = llvm.bitcast %[[cv]] : vector<2xi64> to vector<8xi16> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[b]] : (vector<8xi16>) -> !fir.vector<8:i16> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<8:i16>> + +! CHECK-LLVMIR: %[[v:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[v]] : vector<2xi64> to vector<8xi16> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<8xi16>> + +! CHECK: %[[v:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 +! CHECK: %[[r:.*]] = bitcast <2 x i64> %[[v]] to <8 x i16> +! CHECK: store <8 x i16> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_convert_test_u8i2_array + +!--------- +! vec_cvf +!--------- +! CHECK-LABEL: vec_cvf_test_r4r8 +subroutine vec_cvf_test_r4r8(arg1) + vector(real(8)), intent(in) :: arg1 + vector(real(4)) :: r + r = vec_cvf(arg1) + +! CHECK-FIR: %[[arg:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>> +! CHECK-FIR: %[[carg:.*]] = fir.convert %[[arg]] : (!fir.vector<2:f64>) -> vector<2xf64> +! CHECK-FIR: %[[call:.*]] = fir.call @llvm.ppc.vsx.xvcvdpsp(%[[carg]]) fastmath<contract> : (vector<2xf64>) -> !fir.vector<4:f32> +! CHECK-FIR: %[[ccall:.*]] = fir.convert %[[call]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[bfi:.*]] = llvm.bitcast %[[ccall]] : vector<4xf32> to vector<16xi8> +! CHECK-FIR: %[[sh:.*]] = vector.shuffle %[[bfi]], %[[bfi]] [4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11] : vector<16xi8>, vector<16xi8> +! CHECK-FIR: %[[bif:.*]] = llvm.bitcast %[[sh]] : vector<16xi8> to vector<4xf32> +! CHECK-FIR: %[[r:.*]] = fir.convert %[[bif]] : (vector<4xf32>) -> !fir.vector<4:f32> +! CHECK-FIR: fir.store %[[r]] to %{{.*}} : !fir.ref<!fir.vector<4:f32>> + +! CHECK-LLVMIR: %[[arg:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>> +! CHECK-LLVMIR: %[[call:.*]] = llvm.call @llvm.ppc.vsx.xvcvdpsp(%[[arg]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<2xf64>) -> vector<4xf32> +! CHECK-LLVMIR: %[[b:.*]] = llvm.bitcast %[[call]] : vector<4xf32> to vector<16xi8> +! CHECK-LLVMIR: %[[sh:.*]] = llvm.shufflevector %[[b]], %[[b]] [4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11] : vector<16xi8> +! CHECK-LLVMIR: %[[r:.*]] = llvm.bitcast %[[sh]] : vector<16xi8> to vector<4xf32> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<4xf32>> + +! CHECK: %[[arg:.*]] = load <2 x double>, ptr %{{.*}}, align 16 +! CHECK: %[[call:.*]] = call contract <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %[[arg]]) +! CHECK: %[[b:.*]] = bitcast <4 x float> %[[call]] to <16 x i8> +! CHECK: %[[sh:.*]] = shufflevector <16 x i8> %[[b]], <16 x i8> %[[b]], <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11> +! CHECK: %[[r:.*]] = bitcast <16 x i8> %[[sh]] to <4 x float> +! CHECK: store <4 x float> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_cvf_test_r4r8 + +! CHECK-LABEL: vec_cvf_test_r8r4 +subroutine vec_cvf_test_r8r4(arg1) + vector(real(4)), intent(in) :: arg1 + vector(real(8)) :: r + r = vec_cvf(arg1) + +! CHECK-FIR: %[[arg:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>> +! CHECK-FIR: %[[carg:.*]] = fir.convert %[[arg]] : (!fir.vector<4:f32>) -> vector<4xf32> +! CHECK-FIR: %[[bfi:.*]] = llvm.bitcast %[[carg]] : vector<4xf32> to vector<16xi8> +! CHECK-FIR: %[[sh:.*]] = vector.shuffle %[[bfi]], %[[bfi]] [4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11] : vector<16xi8>, vector<16xi8> +! CHECK-FIR: %[[bif:.*]] = llvm.bitcast %[[sh]] : vector<16xi8> to vector<4xf32> +! CHECK-FIR: %[[call:.*]] = fir.call @llvm.ppc.vsx.xvcvspdp(%[[bif]]) fastmath<contract> : (vector<4xf32>) -> !fir.vector<2:f64> +! CHECK-FIR: fir.store %[[call]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>> + +! CHECK-LLVMIR: %[[arg:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>> +! CHECK-LLVMIR: %[[bfi:.*]] = llvm.bitcast %[[arg]] : vector<4xf32> to vector<16xi8> +! CHECK-LLVMIR: %[[sh:.*]] = llvm.shufflevector %[[bfi]], %[[bfi]] [4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11] : vector<16xi8> +! CHECK-LLVMIR: %[[bif:.*]] = llvm.bitcast %[[sh]] : vector<16xi8> to vector<4xf32> +! CHECK-LLVMIR: %[[r:.*]] = llvm.call @llvm.ppc.vsx.xvcvspdp(%[[bif]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xf32>) -> vector<2xf64> +! CHECK-LLVMIR: llvm.store %[[r]], %{{.*}} : !llvm.ptr<vector<2xf64>> + +! CHECK: %[[arg:.*]] = load <4 x float>, ptr %{{.*}}, align 16 +! CHECK: %[[bfi:.*]] = bitcast <4 x float> %[[arg]] to <16 x i8> +! CHECK: %[[sh:.*]] = shufflevector <16 x i8> %[[bfi]], <16 x i8> %[[bfi]], <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11> +! CHECK: %[[bif:.*]] = bitcast <16 x i8> %[[sh]] to <4 x float> +! CHECK: %[[r:.*]] = call contract <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %[[bif]]) +! CHECK: store <2 x double> %[[r]], ptr %{{.*}}, align 16 +end subroutine vec_cvf_test_r8r4 + + diff --git a/flang/test/Semantics/PowerPC/ppc-vector-intrinsics.f90 b/flang/test/Semantics/PowerPC/ppc-vector-intrinsics.f90 index 7ad44d0..4886615 100644 --- a/flang/test/Semantics/PowerPC/ppc-vector-intrinsics.f90 +++ b/flang/test/Semantics/PowerPC/ppc-vector-intrinsics.f90 @@ -3,6 +3,7 @@ program test vector(integer(4)) :: arg1, arg2, r + vector(real(4)) :: rr integer :: i !ERROR: Actual argument #3 must be a constant expression @@ -14,4 +15,9 @@ program test r = vec_sldw(arg1, arg2, i) !ERROR: Argument #3 must be a constant expression in range 0-3 r = vec_sldw(arg1, arg2, 5) -end + +!ERROR: Actual argument #2 must be a constant expression + rr = vec_ctf(arg1, i) +! ERROR: Argument #2 must be a constant expression in range 0-31 + rr = vec_ctf(arg1, 37) +end program test |