diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 127d308..5e06422 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -81,9 +81,9 @@ def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; -// Operand that is allowed to be a register or a 5 bit immediate. -// This allows us to pick between VSETIVLI and VSETVLI opcodes using the same -// pseudo instructions. +// Operand that is allowed to be a register other than X0, a 5 bit unsigned +// immediate, or -1. -1 means VLMAX. This allows us to pick between VSETIVLI and +// VSETVLI opcodes using the same pseudo instructions. def AVL : RegisterOperand<GPRNoX0> { let OperandNamespace = "RISCVOp"; let OperandType = "OPERAND_AVL"; |