diff options
| -rw-r--r-- | llvm/docs/ReleaseNotes.html | 87 |
1 files changed, 65 insertions, 22 deletions
diff --git a/llvm/docs/ReleaseNotes.html b/llvm/docs/ReleaseNotes.html index a84faba..611d5c8 100644 --- a/llvm/docs/ReleaseNotes.html +++ b/llvm/docs/ReleaseNotes.html @@ -29,12 +29,6 @@ <p>Written by the <a href="http://llvm.org/">LLVM Team</a></p> </div> -<h1 style="color:red">These are in-progress notes for the upcoming LLVM 3.2 -release.<br> -You may prefer the -<a href="http://llvm.org/releases/3.1/docs/ReleaseNotes.html">LLVM 3.1 -Release Notes</a>.</h1> - <!-- *********************************************************************** --> <h2> <a name="intro">Introduction</a> @@ -98,7 +92,9 @@ Release Notes</a>.</h1> <p>In the LLVM 3.2 time-frame, the Clang team has made many improvements. Highlights include:</p> <ul> - <li>...</li> + <li>Improvements to Clang's diagnostics</li> + <li>Support for tls_model attribute</li> + <li>Type safety attributes</li> </ul> <p>For more details about the changes to Clang since the 3.1 release, see the @@ -142,7 +138,8 @@ Release Notes</a>.</h1> <div> -<p>The new LLVM <a href="http://compiler-rt.llvm.org/">compiler-rt project</a> + +<p>The LLVM <a href="http://compiler-rt.llvm.org/">compiler-rt project</a> is a simple library that provides an implementation of the low-level target-specific hooks required by code generation and other runtime components. For example, when compiling for a 32-bit target, converting a @@ -154,7 +151,12 @@ Release Notes</a>.</h1> <p>The 3.2 release has the following notable changes:</p> <ul> - <li>...</li> + <li><a href="http://llvm.org/releases/3.2/tools/clang/docs/ThreadSanitizer.html">ThreadSanitizer (TSan)</a> - data race detector run-time library for C/C++ has been added.</li> + <li>Improvemens to <a href="http://llvm.org/releases/3.2/tools/clang/docs/AddressSanitizer.html">AddressSanitizer</a> including: increasing stack size limit to 256M, + better portability (iOS6,Windows,Android NDK), support for cmake based builds, enhanced error reporting.</li> + + <li>Added support for A6 'Swift' CPU.</li> + <li><code>divsi3</code> function has been enhanced to take advantage of a hardware unsigned divide when it is available.</li> </ul> </div> @@ -235,7 +237,12 @@ Release Notes</a>.</h1> <p>Within the LLVM 3.2 time-frame there were the following highlights:</p> <ul> - <li>...</li> + <li>isl, the integer set library used by Polly, was relicensed to the MIT license</li> + <li>isl based code generation</li> + <li>MIT licensed replacement for CLooG (LGPLv2)</li> + <li>Fine grained option handling (separation of core and border computations, control overhead vs. code size)</li> + <li>Support for FORTRAN and dragonegg</li> + <li>OpenMP code generation fixes</li> </ul> </div> @@ -433,9 +440,9 @@ Release Notes</a>.</h1> <p>LLVM 3.2 includes several major changes and big features:</p> <ul> - <li>...</li> - <li>New NVPTX back-end (replacing existing PTX back-end) based on NVIDIA - sources</li> + <li>Loop Vectorizer.</li> + <li>New implementation of SROA.</li> + <li>New NVPTX back-end (replacing existing PTX back-end) based on NVIDIA sources.</li> </ul> </div> @@ -454,7 +461,10 @@ Release Notes</a>.</h1> <ul> <li>Thread local variables may have a specified TLS model. See the <a href="LangRef.html#globalvars">Language Reference Manual</a>.</li> - <li>...</li> + <li>'TYPE_CODE_FUNCTION_OLD' type code and autoupgrade code for old function attributes format has been removed.</li> + <li>Internal representation of the Attributes class has been converted into a pointer to an + opaque object that's uniqued by and stored in the LLVMContext object. + The Attributes class then becomes a thin wrapper around this opaque object.</li> </ul> </div> @@ -492,7 +502,7 @@ Release Notes</a>.</h1> <ul> <li>The inner most loops must have a single basic block.</li> <li>The number of iterations are known before the loop starts to execute.</li> - <li>The loop counter needs to be incrimented by one.</li> + <li>The loop counter needs to be incremented by one.</li> <li>The loop trip count <b>can</b> be a variable.</li> <li>Loops do <b>not</b> need to start at zero.</li> <li>The induction variable can be used inside the loop.</li> @@ -527,8 +537,19 @@ Release Notes</a>.</h1> <a href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro to the LLVM MC Project Blog Post</a>.</p> -<ul> - <li>...</li> +<ul> + <li> Added support for following assembler directives: <code>.ifb</code>, <code>.ifnb</code>, <code>.ifc</code>, + <code>.ifnc</code>, <code>.purgem</code>, <code>.rept</code> and <code>.version</code> (ELF) as well as Darwin specific + <code>.pushsection</code>, <code>.popsection</code> and <code>.previous</code> .</li> + <li>Enhanced handling of <code>.lcomm directive</code>.</li> + <li>MS style inline assembler: added implementation of the offset and TYPE operators.</li> + <li>Targets can specify minimum supported NOP size for NOP padding.</li> + <li>ELF improvements: added support for generating ELF objects on Windows.</li> + <li>MachO improvements: symbol-difference variables are marked as N_ABS, added direct-to-object attribute for data-in-code markers.</li> + <li>Added support for annotated disassembly output for x86 and arm targets.</li> + <li>Arm support has been improved by adding support for ARM TARGET2 relocation + and fixing hadling of ARM-style "$d.*" labels.</li> + <li>Implemented local-exec TLS on PowerPC.</li> </ul> </div> @@ -591,7 +612,7 @@ Release Notes</a>.</h1> <p>New features and major changes in the X86 target include:</p> <ul> - <li>...</li> + <li>Small codegen optimizations, especially for AVX2.</li> </ul> </div> @@ -606,7 +627,7 @@ Release Notes</a>.</h1> <p>New features of the ARM target include:</p> <ul> - <li>...</li> + <li>Support and performance tuning for the A6 'Swift' CPU.</li> </ul> <!--_________________________________________________________________________--> @@ -643,7 +664,31 @@ Release Notes</a>.</h1> <p>New features and major changes in the MIPS target include:</p> <ul> - <li>...</li> + <li>Integrated assembler support: + MIPS32 works for both PIC and static, known limitation is the PR14456 where + R_MIPS_GPREL16 relocation is generated with the wrong addend. + MIPS64 support is incomplete, for example exception handling is not working.</li> + <li>Support for fast calling convention has been added.</li> + <li>Support for Android MIPS toolchain has been added to clang driver.</li> + <li>Added clang driver support for MIPS N32 ABI through "-mabi=n32" option.</li> + <li>MIPS32 and MIPS64 disassembler has been implemented.</li> + <li>Support for compiling programs with large GOTs (exceeding 64kB in size) has be added + through llc option "-mxgot".</li> + <li>Experimental support for MIPS32 DSP intrinsics has been added</li> + <li>Experimental support for MIPS16 with following limitations: only soft float is supported, + C++ exceptions are not supported, large stack frames (> 32000 bytes) are not supported, + direct object code emission is not supported yet (only .s).</li> + <li>Standalone assembler (llvm-mc): implementation is in progress and assembler should be + considered experimental</li> + <li>All classic JIT and MCJIT tests pass on Little and Big Endian MIPS32 platforms.</li> + <li>Inline asm support: all common constraints and operand modifiers + have been implemented.</li> + <li>Tail call optimization support has been added, use llc option "-enable-mips-tail-calls" + or clang options "-mllvm -enable-mips-tail-calls"to enable it.</li> + <li>Improved register allocation by removing registers 'FP', 'GP', 'RA' and 'AT' from the list of reserved registers.</li> + <li>Long branch expansion pass has been implemented, which expands branch + instructions with offsets that do not fit in the 16-bit field.</li> + <li>Cavium Octeon II board is used for testing builds (llvm-mips-linux builder).</li> </ul> </div> @@ -655,7 +700,6 @@ Release Notes</a>.</h1> <div> -<ul> <p>Many fixes and changes across LLVM (and Clang) for better compliance with the 64-bit PowerPC ELF Application Binary Interface, interoperability with GCC, and overall 64-bit PowerPC support. Some highlights include:</p> @@ -684,7 +728,6 @@ Release Notes</a>.</h1> <p>There have also been code generation improvements for both 32- and 64-bit code. Instruction scheduling support for the Freescale e500mc and e5500 cores has been added.</p> -</ul> </div> |