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authorAndrzej WarzyƄski <andrzej.warzynski@arm.com>2023-12-06 21:35:23 +0000
committerGitHub <noreply@github.com>2023-12-06 21:35:23 +0000
commitfb62a18615d28694f1a16a3e23915190703a2e98 (patch)
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parent03c2f5d8bbcf31239a631d9343ac7f4b6b3094c1 (diff)
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[mlir][ArmSME] Update docs (#74527)
Diffstat (limited to 'mlir')
-rw-r--r--mlir/docs/Dialects/ArmSME.md28
1 files changed, 22 insertions, 6 deletions
diff --git a/mlir/docs/Dialects/ArmSME.md b/mlir/docs/Dialects/ArmSME.md
index 505b529..7326150 100644
--- a/mlir/docs/Dialects/ArmSME.md
+++ b/mlir/docs/Dialects/ArmSME.md
@@ -1,13 +1,29 @@
# 'ArmSME' Dialect
-[TOC]
+Basic dialect to target Arm SME.
+
+This dialect defines custom and LLVM IR intrinsic operations that are used to
+target Arm Scalable Matrix Extension. Through the available conversion and
+ArmSME passes you can, for example, lower a
+[linalg.matmul](https://mlir.llvm.org/docs/Dialects/Linalg/#linalgmatmul-linalgmatmulop)
+opereation to Arm SME
+[FMOPA](https://developer.arm.com/documentation/ddi0602/2023-03/SME-Instructions/FMOPA--widening---Half-precision-floating-point-sum-of-outer-products-and-accumulate-)
+(floating-point outer product) operations. See one of the in-tree end-to-end
+integration tests for reference:
+
+* [Linalg/CPU/ArmSME/matmul.mlir](https://github.com/llvm/llvm-project/blob/main/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir)
+* [Vector/CPU/ArmSME/test-outerproduct-f64.mlir](https://github.com/llvm/llvm-project/blob/main/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir)
-Basic dialect to target Arm SME architectures This dialect contains the
-definitions necessary to target Arm SME scalable matrix operations.
+These tests are run "post-commit" by the
+[clang-aarch64-sve-vla](https://lab.llvm.org/buildbot/#/builders/197) LLVM
+BuildBot worker.
-## References
-* https://developer.arm.com/documentation/ddi0616
-* https://developer.arm.com/documentation/ddi0602/2023-03/SME-Instructions
+**References:**
+
+* [The Scalable Matrix Extension (SME), for Armv9-A](https://developer.arm.com/documentation/ddi0616)
+* [A64 -- SME Instructions (alphabetic order)](https://developer.arm.com/documentation/ddi0602/2023-03/SME-Instructions)
+
+[TOC]
## Operations