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| author | Christian Sigg <csigg@google.com> | 2021-03-19 00:22:50 -0700 |
|---|---|---|
| committer | Christian Sigg <csigg@google.com> | 2021-03-19 00:24:10 -0700 |
| commit | a825fb2c07337cc2c84783558e91416e07adcf42 (patch) | |
| tree | 2ab4d4673c0df3b5ece19a061361d749646a65b9 /mlir/test/lit.site.cfg.py.in | |
| parent | 4ee4f9bf4ae49df25b46351a0bfca3a36e7bf82d (diff) | |
| download | llvm-a825fb2c07337cc2c84783558e91416e07adcf42.zip llvm-a825fb2c07337cc2c84783558e91416e07adcf42.tar.gz llvm-a825fb2c07337cc2c84783558e91416e07adcf42.tar.bz2 | |
[mlir] Remove mlir-rocm-runner
This change combines for ROCm what was done for CUDA in D97463, D98203, D98360, and D98396.
I did not try to compile SerializeToHsaco.cpp or test mlir/test/Integration/GPU/ROCM because I don't have an AMD card. I fixed the things that had obvious bit-rot though.
Reviewed By: whchung
Differential Revision: https://reviews.llvm.org/D98447
Diffstat (limited to 'mlir/test/lit.site.cfg.py.in')
| -rw-r--r-- | mlir/test/lit.site.cfg.py.in | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in index 0015c13..dbc8460 100644 --- a/mlir/test/lit.site.cfg.py.in +++ b/mlir/test/lit.site.cfg.py.in @@ -39,7 +39,6 @@ config.build_examples = @LLVM_BUILD_EXAMPLES@ config.run_cuda_tests = @MLIR_CUDA_CONVERSIONS_ENABLED@ config.enable_cuda_runner = @MLIR_CUDA_RUNNER_ENABLED@ config.run_rocm_tests = @MLIR_ROCM_CONVERSIONS_ENABLED@ -config.rocm_wrapper_library_dir = "@MLIR_ROCM_WRAPPER_LIBRARY_DIR@" config.enable_rocm_runner = @MLIR_ROCM_RUNNER_ENABLED@ config.spirv_wrapper_library_dir = "@MLIR_SPIRV_WRAPPER_LIBRARY_DIR@" config.enable_spirv_cpu_runner = @MLIR_SPIRV_CPU_RUNNER_ENABLED@ |