[mlir] Data layout for integer and float types

Add support for integer and float types into the data layout subsystem with
default logic similar to LLVM IR. Given the flexibility of the sybsystem, the
logic can be easily overwritten by operations if necessary. This provides the
connection necessary, e.g., for the GPU target where alignment requirements for
integers and floats differ from those provided by default (although still
compatible with the LLVM IR model). Previously, it was impossible to use
non-default alignment requirements for integer and float types, which could
lead to incorrect address and size calculations when targeting GPUs.

Depends On D120737

Reviewed By: wsmoses

Differential Revision: https://reviews.llvm.org/D120739

2 files changed, 102 insertions, 0 deletions

diff --git a/mlir/test/Interfaces/DataLayoutInterfaces/query.mlir b/mlir/test/Interfaces/DataLayoutInterfaces/query.mlir
index c7f2582..bc3e66c 100644
--- a/mlir/test/Interfaces/DataLayoutInterfaces/query.mlir
+++ b/mlir/test/Interfaces/DataLayoutInterfaces/query.mlir
@@ -194,3 +194,84 @@ func @nested_combine_all() {
   >}: () -> ()
   return
 }
+
+// CHECK-LABEL: @integers
+func @integers() {
+  "test.op_with_data_layout"() ({
+    // CHECK: alignment = 8
+    // CHECK: bitsize = 32
+    // CHECK: preferred = 8
+    "test.data_layout_query"() : () -> i32
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 56
+    // CHECK: preferred = 16
+    "test.data_layout_query"() : () -> i56
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 64
+    // CHECK: preferred = 16
+    "test.data_layout_query"() : () -> i64
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 128
+    // CHECK: preferred = 16
+    "test.data_layout_query"() : () -> i128
+    "test.maybe_terminator"() : () -> ()
+  }) { dlti.dl_spec = #dlti.dl_spec<
+      #dlti.dl_entry<i32, dense<64> : vector<1xi32>>,
+      #dlti.dl_entry<i64, dense<128> : vector<1xi32>>
+    >} : () -> ()
+  "test.op_with_data_layout"() ({
+    // CHECK: alignment = 8
+    // CHECK: bitsize = 32
+    // CHECK: preferred = 16
+    "test.data_layout_query"() : () -> i32
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 56
+    // CHECK: preferred = 32
+    "test.data_layout_query"() : () -> i56
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 64
+    // CHECK: preferred = 32
+    "test.data_layout_query"() : () -> i64
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 128
+    // CHECK: preferred = 32
+    "test.data_layout_query"() : () -> i128
+    "test.maybe_terminator"() : () -> ()
+  }) { dlti.dl_spec = #dlti.dl_spec<
+      #dlti.dl_entry<i32, dense<[64, 128]> : vector<2xi32>>,
+      #dlti.dl_entry<i64, dense<[128, 256]> : vector<2xi32>>
+    >} : () -> ()
+  return
+}
+
+func @floats() {
+  "test.op_with_data_layout"() ({
+    // CHECK: alignment = 8
+    // CHECK: bitsize = 32
+    // CHECK: preferred = 8
+    "test.data_layout_query"() : () -> f32
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 80
+    // CHECK: preferred = 16
+    "test.data_layout_query"() : () -> f80
+    "test.maybe_terminator"() : () -> ()
+  }) { dlti.dl_spec = #dlti.dl_spec<
+      #dlti.dl_entry<f32, dense<64> : vector<1xi32>>,
+      #dlti.dl_entry<f80, dense<128> : vector<1xi32>>
+    >} : () -> ()
+  "test.op_with_data_layout"() ({
+    // CHECK: alignment = 8
+    // CHECK: bitsize = 32
+    // CHECK: preferred = 16
+    "test.data_layout_query"() : () -> f32
+    // CHECK: alignment = 16
+    // CHECK: bitsize = 80
+    // CHECK: preferred = 32
+    "test.data_layout_query"() : () -> f80
+    "test.maybe_terminator"() : () -> ()
+  }) { dlti.dl_spec = #dlti.dl_spec<
+      #dlti.dl_entry<f32, dense<[64, 128]> : vector<2xi32>>,
+      #dlti.dl_entry<f80, dense<[128, 256]> : vector<2xi32>>
+    >} : () -> ()
+  return
+}
diff --git a/mlir/test/Interfaces/DataLayoutInterfaces/types.mlir b/mlir/test/Interfaces/DataLayoutInterfaces/types.mlir
index 8c1fe50..64e5a35 100644
--- a/mlir/test/Interfaces/DataLayoutInterfaces/types.mlir
+++ b/mlir/test/Interfaces/DataLayoutInterfaces/types.mlir
@@ -7,6 +7,27 @@ module attributes { dlti.dl_spec = #dlti.dl_spec<
 
 // -----
 
+// expected-error@below {{expected a dense i32 elements attribute}}
+module attributes {dlti.dl_spec = #dlti.dl_spec<
+#dlti.dl_entry<i32, dense<[64,128]> : vector<2xi64>>>
+} {}
+
+// -----
+
+// expected-error@below {{expected 1 or 2 elements}}
+module attributes {dlti.dl_spec = #dlti.dl_spec<
+#dlti.dl_entry<i32, dense<[64,64,64]> : vector<3xi32>>>
+} {}
+
+// -----
+
+// expected-error@below {{preferred alignment is expected to be greater than or equal to the abi alignment}}
+module attributes {dlti.dl_spec = #dlti.dl_spec<
+#dlti.dl_entry<i32, dense<[64,32]> : vector<2xi32>>>
+} {}
+
+// -----
+
 // expected-error@below {{the 'test' dialect does not support identifier data layout entries}}
 "test.op_with_data_layout"() { dlti.dl_spec = #dlti.dl_spec<
   #dlti.dl_entry<index, 32>,