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author | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2020-07-07 11:29:12 +0100 |
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committer | Kerry McLaughlin <kerry.mclaughlin@arm.com> | 2020-07-07 11:47:10 +0100 |
commit | cdf2eef613f7d6949e2929b316925c3553a8e3d0 (patch) | |
tree | 17b5c37092fb2477f33483764784e6c978afebbe /llvm | |
parent | 2953ac0975bc7e5dbe61fbd6538f02487efa62d2 (diff) | |
download | llvm-cdf2eef613f7d6949e2929b316925c3553a8e3d0.zip llvm-cdf2eef613f7d6949e2929b316925c3553a8e3d0.tar.gz llvm-cdf2eef613f7d6949e2929b316925c3553a8e3d0.tar.bz2 |
[SVE][CodeGen] Legalisation of unpredicated store instructions
Summary:
When splitting a store of a scalable type, the new address is
calculated in SplitVecOp_STORE using a vscale and an add instruction.
Reviewers: sdesmalen, efriedma, david-arm
Reviewed By: david-arm
Subscribers: tschuett, hiraditya, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D83041
Diffstat (limited to 'llvm')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 23 | ||||
-rw-r--r-- | llvm/test/CodeGen/AArch64/sve-split-store.ll | 53 |
2 files changed, 68 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index cacc2df..96c3a71 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -2490,7 +2490,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized()) return TLI.scalarizeVectorStore(N, DAG); - unsigned IncrementSize = LoMemVT.getSizeInBits()/8; + unsigned IncrementSize = LoMemVT.getSizeInBits().getKnownMinSize() / 8; if (isTruncating) Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT, @@ -2499,17 +2499,24 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags, AAInfo); - // Increment the pointer to the other half. - Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize); + MachinePointerInfo MPI; + if (LoMemVT.isScalableVector()) { + SDValue BytesIncrement = DAG.getVScale( + DL, Ptr.getValueType(), + APInt(Ptr.getValueSizeInBits().getFixedSize(), IncrementSize)); + MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace()); + Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, BytesIncrement); + } else { + MPI = N->getPointerInfo().getWithOffset(IncrementSize); + // Increment the pointer to the other half. + Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize); + } if (isTruncating) - Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, - N->getPointerInfo().getWithOffset(IncrementSize), + Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, MPI, HiMemVT, Alignment, MMOFlags, AAInfo); else - Hi = DAG.getStore(Ch, DL, Hi, Ptr, - N->getPointerInfo().getWithOffset(IncrementSize), - Alignment, MMOFlags, AAInfo); + Hi = DAG.getStore(Ch, DL, Hi, Ptr, MPI, Alignment, MMOFlags, AAInfo); return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); } diff --git a/llvm/test/CodeGen/AArch64/sve-split-store.ll b/llvm/test/CodeGen/AArch64/sve-split-store.ll new file mode 100644 index 0000000..2fba040 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-split-store.ll @@ -0,0 +1,53 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +define void @store_promote_4i8(<vscale x 4 x i8> %data, <vscale x 4 x i8>* %a) { +; CHECK-LABEL: store_promote_4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: st1b { z0.s }, p0, [x0] +; CHECK-NEXT: ret + store <vscale x 4 x i8> %data, <vscale x 4 x i8>* %a + ret void +} + +define void @store_split_i16(<vscale x 16 x i16> %data, <vscale x 16 x i16>* %a) { +; CHECK-LABEL: store_split_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: st1h { z1.h }, p0, [x0, #1, mul vl] +; CHECK-NEXT: st1h { z0.h }, p0, [x0] +; CHECK-NEXT: ret + store <vscale x 16 x i16> %data, <vscale x 16 x i16>* %a + ret void +} + +define void @store_split_16i32(<vscale x 16 x i32> %data, <vscale x 16 x i32>* %a) { +; CHECK-LABEL: store_split_16i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: st1w { z3.s }, p0, [x0, #3, mul vl] +; CHECK-NEXT: st1w { z2.s }, p0, [x0, #2, mul vl] +; CHECK-NEXT: st1w { z1.s }, p0, [x0, #1, mul vl] +; CHECK-NEXT: st1w { z0.s }, p0, [x0] +; CHECK-NEXT: ret + store <vscale x 16 x i32> %data, <vscale x 16 x i32>* %a + ret void +} + +define void @store_split_16i64(<vscale x 16 x i64> %data, <vscale x 16 x i64>* %a) { +; CHECK-LABEL: store_split_16i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] +; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] +; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] +; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] +; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] +; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] +; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] +; CHECK-NEXT: st1d { z0.d }, p0, [x0] +; CHECK-NEXT: ret + store <vscale x 16 x i64> %data, <vscale x 16 x i64>* %a + ret void +} |