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| author | Freddy Ye <freddy.ye@intel.com> | 2022-10-08 14:27:06 +0800 |
|---|---|---|
| committer | Tobias Hieta <tobias@hieta.se> | 2022-10-10 08:49:16 +0200 |
| commit | bd5722b87b5aa1b8286762af7f29b6aae669dee1 (patch) | |
| tree | dd6ae7327641f98d57778359364393ac88d01d2a /llvm | |
| parent | 73ea64f30411bcb9a2f32649a49d4c23780ee045 (diff) | |
| download | llvm-bd5722b87b5aa1b8286762af7f29b6aae669dee1.zip llvm-bd5722b87b5aa1b8286762af7f29b6aae669dee1.tar.gz llvm-bd5722b87b5aa1b8286762af7f29b6aae669dee1.tar.bz2 | |
[X86] Remove AVX512VP2INTERSECT from Sapphire Rapids.
For more details, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D135509
(cherry picked from commit 566c277c64f8f76d8911aa5fd931903a357ed7be)
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Support/X86TargetParser.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 1 |
2 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index 2567f3e..0daaa6d 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -203,10 +203,10 @@ constexpr FeatureBitset FeaturesTigerlake = FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; constexpr FeatureBitset FeaturesSapphireRapids = FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | - FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT | - FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B | - FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK | - FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG; + FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE | + FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | + FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | + FeatureWAITPKG; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. @@ -367,7 +367,7 @@ constexpr ProcInfo Processors[] = { // Tigerlake microarchitecture based processors. { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, // Sapphire Rapids microarchitecture based processors. - { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, + { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids }, // Alderlake microarchitecture based processors. { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake }, // Knights Landing processor. diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index fa0a6bd..f98916e 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -909,7 +909,6 @@ def ProcessorFeatures { FeatureTSXLDTRK, FeatureENQCMD, FeatureSHSTK, - FeatureVP2INTERSECT, FeatureMOVDIRI, FeatureMOVDIR64B, FeatureUINTR]; |