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| author | Wang Pengcheng <wangpengcheng.pp@bytedance.com> | 2024-04-17 21:47:29 +0800 |
|---|---|---|
| committer | Wang Pengcheng <wangpengcheng.pp@bytedance.com> | 2024-04-17 21:47:29 +0800 |
| commit | 7d1b70a3960cdacfa4d7531531a9a921dadd3d88 (patch) | |
| tree | ac207bdf9fcb3c3656deafb734acd8f03b40c8db /llvm/test/Transforms/InstCombine/vector-urem.ll | |
| parent | c9d96c0d77b67c208aaf7f8f2554f972baa412d2 (diff) | |
| parent | e77f6742143d71161f3f1161270648c9b95b2137 (diff) | |
| download | llvm-users/wangpc-pp/spr/riscv-dont-use-v0-directly-in-patterns.zip llvm-users/wangpc-pp/spr/riscv-dont-use-v0-directly-in-patterns.tar.gz llvm-users/wangpc-pp/spr/riscv-dont-use-v0-directly-in-patterns.tar.bz2 | |
Rebase on #88868users/wangpc-pp/spr/riscv-dont-use-v0-directly-in-patterns
Created using spr 1.3.6-beta.1
Diffstat (limited to 'llvm/test/Transforms/InstCombine/vector-urem.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vector-urem.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/Transforms/InstCombine/vector-urem.ll b/llvm/test/Transforms/InstCombine/vector-urem.ll index d5c7747..627789a 100644 --- a/llvm/test/Transforms/InstCombine/vector-urem.ll +++ b/llvm/test/Transforms/InstCombine/vector-urem.ll @@ -19,11 +19,11 @@ define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) { ret <4 x i32> %1 } -define <4 x i32> @test_v4i32_const_pow2_undef(<4 x i32> %a0) { -; CHECK-LABEL: @test_v4i32_const_pow2_undef( +define <4 x i32> @test_v4i32_const_pow2_poison(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_const_pow2_poison( ; CHECK-NEXT: ret <4 x i32> poison ; - %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 undef> + %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 poison> ret <4 x i32> %1 } @@ -37,13 +37,13 @@ define <4 x i32> @test_v4i32_one(<4 x i32> %a0) { ret <4 x i32> %1 } -define <4 x i32> @test_v4i32_one_undef(<4 x i32> %a0) { -; CHECK-LABEL: @test_v4i32_one_undef( +define <4 x i32> @test_v4i32_one_poison(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_one_poison( ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> ; CHECK-NEXT: ret <4 x i32> [[TMP2]] ; - %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 undef>, %a0 + %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 poison>, %a0 ret <4 x i32> %1 } @@ -71,10 +71,10 @@ define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) { ret <4 x i32> %1 } -define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) { -; CHECK-LABEL: @test_v4i32_negconst_undef( +define <4 x i32> @test_v4i32_negconst_poison(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_negconst_poison( ; CHECK-NEXT: ret <4 x i32> poison ; - %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef> + %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 poison> ret <4 x i32> %1 } |