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authorNikita Popov <npopov@redhat.com>2023-07-28 14:21:00 +0200
committerNikita Popov <npopov@redhat.com>2023-07-28 16:39:44 +0200
commit279c2971951c2ea58a2bd1e6687ce61451f9d329 (patch)
tree6882815aed905409c1250f609fac36722f6e1933 /llvm/test/ThinLTO
parenta54320392cd99bd23f991a487ec9a45e13f9cfb7 (diff)
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[ThinLTO] Use module hash instead of module ID for cache key
This is a followup to D151165. Instead of using the module ID, use the module hash for sorting the import list. The module hash is what will actually be included in the hash. This has the advantage of being independent of the module order, which is something that Rust relies on. A caveat here is that the test doesn't quite work for linkonce_odr functions, because the function may be imported from two different modules, and the first one on the llvm-lto2 command line gets picked (rather than, say, the prevailing copy). This doesn't really matter for Rust's purposes (because it does not use linkonce_odr linkage), but may still be worth addressing. For now I'm using a variant of the test using internal instead of linkonce_odr functions. Differential Revision: https://reviews.llvm.org/D156525
Diffstat (limited to 'llvm/test/ThinLTO')
-rw-r--r--llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll11
-rw-r--r--llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll11
-rw-r--r--llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll24
3 files changed, 46 insertions, 0 deletions
diff --git a/llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll b/llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll
new file mode 100644
index 0000000..92247d1
--- /dev/null
+++ b/llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll
@@ -0,0 +1,11 @@
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f1() {
+ call void @internal()
+ ret void
+}
+
+define internal void @internal() {
+ ret void
+}
diff --git a/llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll b/llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll
new file mode 100644
index 0000000..281905f
--- /dev/null
+++ b/llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll
@@ -0,0 +1,11 @@
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f2() {
+ call void @internal()
+ ret void
+}
+
+define internal void @internal() {
+ ret void
+}
diff --git a/llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll b/llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll
new file mode 100644
index 0000000..8871750
--- /dev/null
+++ b/llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll
@@ -0,0 +1,24 @@
+; RUN: rm -rf %t && mkdir -p %t
+; RUN: opt -module-hash -module-summary %s -o %t/t.bc
+; RUN: opt -module-hash -module-summary %S/Inputs/cache-import-lists3.ll -o %t/a.bc
+; RUN: opt -module-hash -module-summary %S/Inputs/cache-import-lists4.ll -o %t/b.bc
+
+; Tests that the hash for t is insensitive to the order of the modules.
+
+; RUN: llvm-lto2 run -cache-dir %t/cache -o %t.o %t/t.bc %t/a.bc %t/b.bc -r=%t/t.bc,main,plx -r=%t/t.bc,f1,lx -r=%t/t.bc,f2,lx -r=%t/a.bc,f1,plx -r=%t/b.bc,f2,plx
+; RUN: ls %t/cache | count 3
+
+; RUN: llvm-lto2 run -cache-dir %t/cache -o %t.o %t/b.bc %t/a.bc %t/t.bc -r=%t/t.bc,main,plx -r=%t/t.bc,f1,lx -r=%t/t.bc,f2,lx -r=%t/a.bc,f1,plx -r=%t/b.bc,f2,plx
+; RUN: ls %t/cache | count 3
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @main() {
+ call void @f1()
+ call void @f2()
+ ret void
+}
+
+declare void @f1()
+declare void @f2()