[DX] Support pipeline state masks (#66425)

The DXContainer pipeline state information encodes a bunch of mask
vectors that are used to track things about the inputs and outputs from
each shader.

This adds support for reading and writing them throught he YAML test
interfaces. The writing logic in MC is extremely primitive and we'll
want to revisit the API for that, but since I'm not sure how we'll want
to generate the mask bits from DXIL during code generation I didn't want
to spend too much time on the API.

Fixes #59479

20 files changed, 810 insertions, 82 deletions

diff --git a/llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml b/llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
new file mode 100644
index 0000000..713fbc6
--- /dev/null
+++ b/llvm/test/ObjectYAML/DXContainer/DomainMaskVectors.yaml
@@ -0,0 +1,200 @@
+# RUN: yaml2obj %s | obj2yaml | FileCheck %s
+--- !dxcontainer
+Header:
+  Hash:            [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
+                     0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+  Version:
+    Major:           1
+    Minor:           0
+  FileSize:        4616
+  PartCount:       8
+  PartOffsets:     [ 64, 80, 140, 200, 580, 952, 2756, 2784 ]
+Parts:
+  - Name:            SFI0
+    Size:            8
+    Flags:
+      Doubles:         false
+      ComputeShadersPlusRawAndStructuredBuffers: false
+      UAVsAtEveryStage: false
+      Max64UAVs:       false
+      MinimumPrecision: false
+      DX11_1_DoubleExtensions: false
+      DX11_1_ShaderExtensions: false
+      LEVEL9ComparisonFiltering: false
+      TiledResources:  false
+      StencilRef:      false
+      InnerCoverage:   false
+      TypedUAVLoadAdditionalFormats: false
+      ROVs:            false
+      ViewportAndRTArrayIndexFromAnyShaderFeedingRasterizer: false
+      WaveOps:         false
+      Int64Ops:        false
+      ViewID:          true
+      Barycentrics:    false
+      NativeLowPrecision: false
+      ShadingRate:     false
+      Raytracing_Tier_1_1: false
+      SamplerFeedback: false
+      AtomicInt64OnTypedResource: false
+      AtomicInt64OnGroupShared: false
+      DerivativesInMeshAndAmpShaders: false
+      ResourceDescriptorHeapIndexing: false
+      SamplerDescriptorHeapIndexing: false
+      RESERVED:        false
+      AtomicInt64OnHeapResource: false
+      AdvancedTextureOps: false
+      WriteableMSAATextures: false
+      NextUnusedBit:   false
+  - Name:            ISG1
+    Size:            52
+  - Name:            OSG1
+    Size:            52
+  - Name:            PSG1
+    Size:            372
+  - Name:            PSV0
+    Size:            364
+    PSVInfo:
+      Version:         2
+      ShaderStage:     4
+      InputControlPointCount: 16
+      OutputPositionPresent: 1
+      TessellatorDomain: 3
+      MinimumWaveLaneCount: 0
+      MaximumWaveLaneCount: 4294967295
+      UsesViewID:      1
+      SigPatchConstOrPrimVectors: 7
+      SigInputVectors: 1
+      SigOutputVectors: [ 1, 0, 0, 0 ]
+      NumThreadsX:     0
+      NumThreadsY:     0
+      NumThreadsZ:     0
+      ResourceStride:  24
+      Resources:
+        - Type:            2
+          Space:           0
+          LowerBound:      0
+          UpperBound:      0
+          Kind:            13
+          Flags:           0
+      SigInputElements:
+        - Name:            AAA_HSFoo
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            3
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          0
+      SigOutputElements:
+        - Name:            ''
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Position
+          ComponentType:   Float32
+          Interpolation:   LinearNoperspective
+          DynamicMask:     0x0
+          Stream:          0
+      SigPatchOrPrimElements:
+        - Name:            ''
+          Indices:         [ 0, 1, 2, 3 ]
+          StartRow:        0
+          Cols:            1
+          StartCol:        3
+          Allocated:       true
+          Kind:            TessFactor
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            ''
+          Indices:         [ 0, 1 ]
+          StartRow:        4
+          Cols:            1
+          StartCol:        3
+          Allocated:       true
+          Kind:            InsideTessFactor
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            AAA
+          Indices:         [ 0 ]
+          StartRow:        6
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            BBB
+          Indices:         [ 0, 1, 2 ]
+          StartRow:        0
+          Cols:            3
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+      OutputVectorMasks:
+        - [ 0x1 ]
+        - [  ]
+        - [  ]
+        - [  ]
+      InputOutputMap:
+        - [ 0x0, 0xD, 0x0, 0x0 ]
+        - [  ]
+        - [  ]
+        - [  ]
+      PatchOutputMap:  [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 
+                         0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
+                         0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 ]
+  - Name:            STAT
+    Size:            1796
+  - Name:            HASH
+    Size:            20
+    Hash:
+      IncludesSource:  false
+      Digest:          [ 0xD4, 0x48, 0xCB, 0xFE, 0xF9, 0xCD, 0x92, 0x7B, 
+                         0xBD, 0x2B, 0x9A, 0x9D, 0xB4, 0x6F, 0x3E, 0x83 ]
+  - Name:            DXIL
+    Size:            24
+    Program:
+      MajorVersion:    6
+      MinorVersion:    1
+      ShaderKind:      4
+      Size:            6
+      DXILMajorVersion: 1
+      DXILMinorVersion: 1
+      DXILSize:        0
+...
+
+# Verify the vector sizes and ViewID use.
+# CHECK: UsesViewID:      1
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 7
+# CHECK-NEXT: SigInputVectors: 1
+# CHECK-NEXT: SigOutputVectors: [ 1, 0, 0, 0 ]
+
+# Verify the vector mask encodings.
+# CHECK: OutputVectorMasks:
+# CHECK-NEXT:   - [ 0x1 ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [ 0x0, 0xD, 0x0, 0x0 ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: PatchOutputMap:  [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 
+# CHECK-NEXT:                    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
+# CHECK-NEXT:                    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 ]
diff --git a/llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml b/llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml
new file mode 100644
index 0000000..bf29d08
--- /dev/null
+++ b/llvm/test/ObjectYAML/DXContainer/GeometryMaskVectors.yaml
@@ -0,0 +1,174 @@
+# RUN: yaml2obj %s | obj2yaml | FileCheck %s
+--- !dxcontainer
+Header:
+  Hash:            [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
+                     0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+  Version:
+    Major:           1
+    Minor:           0
+  FileSize:        3836
+  PartCount:       7
+  PartOffsets:     [ 60, 76, 204, 292, 584, 2092, 2120 ]
+Parts:
+  - Name:            SFI0
+    Size:            8
+    Flags:
+      Doubles:         false
+      ComputeShadersPlusRawAndStructuredBuffers: false
+      UAVsAtEveryStage: false
+      Max64UAVs:       false
+      MinimumPrecision: false
+      DX11_1_DoubleExtensions: false
+      DX11_1_ShaderExtensions: false
+      LEVEL9ComparisonFiltering: false
+      TiledResources:  false
+      StencilRef:      false
+      InnerCoverage:   false
+      TypedUAVLoadAdditionalFormats: false
+      ROVs:            false
+      ViewportAndRTArrayIndexFromAnyShaderFeedingRasterizer: false
+      WaveOps:         false
+      Int64Ops:        false
+      ViewID:          true
+      Barycentrics:    false
+      NativeLowPrecision: false
+      ShadingRate:     false
+      Raytracing_Tier_1_1: false
+      SamplerFeedback: false
+      AtomicInt64OnTypedResource: false
+      AtomicInt64OnGroupShared: false
+      DerivativesInMeshAndAmpShaders: false
+      ResourceDescriptorHeapIndexing: false
+      SamplerDescriptorHeapIndexing: false
+      RESERVED:        false
+      AtomicInt64OnHeapResource: false
+      AdvancedTextureOps: false
+      WriteableMSAATextures: false
+      NextUnusedBit:   false
+  - Name:            ISG1
+    Size:            120
+  - Name:            OSG1
+    Size:            80
+  - Name:            PSV0
+    Size:            284
+    PSVInfo:
+      Version:         2
+      ShaderStage:     2
+      InputPrimitive:  3
+      OutputTopology:  1
+      OutputStreamMask: 3
+      OutputPositionPresent: 0
+      MinimumWaveLaneCount: 0
+      MaximumWaveLaneCount: 4294967295
+      UsesViewID:      1
+      MaxVertexCount:  3
+      SigInputVectors: 3
+      SigOutputVectors: [ 1, 1, 0, 0 ]
+      NumThreadsX:     0
+      NumThreadsY:     0
+      NumThreadsZ:     0
+      ResourceStride:  24
+      Resources:       []
+      SigInputElements:
+        - Name:            ''
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Position
+          ComponentType:   Float32
+          Interpolation:   LinearNoperspective
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            AAA
+          Indices:         [ 2 ]
+          StartRow:        1
+          Cols:            2
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            AAA
+          Indices:         [ 3 ]
+          StartRow:        2
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          0
+      SigOutputElements:
+        - Name:            BBB
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            CCC
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          1
+      SigPatchOrPrimElements: []
+      OutputVectorMasks:
+        - [ 0xE ]
+        - [ 0x5 ]
+        - [  ]
+        - [  ]
+      InputOutputMap:
+        - [ 0x2, 0x4, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+        - [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0x4, 0x8 ]
+        - [  ]
+        - [  ]
+  - Name:            STAT
+    Size:            1500
+  - Name:            HASH
+    Size:            20
+    Hash:
+      IncludesSource:  false
+      Digest:          [ 0x10, 0xA2, 0x84, 0xA5, 0x76, 0xA6, 0x28, 0x82, 
+                         0x21, 0x39, 0x1, 0xE0, 0x53, 0x19, 0xBE, 0x79 ]
+  - Name:            DXIL
+    Size:            24
+    Program:
+      MajorVersion:    6
+      MinorVersion:    1
+      ShaderKind:      2
+      Size:            6
+      DXILMajorVersion: 1
+      DXILMinorVersion: 1
+      DXILSize:        0
+...
+
+# Verify the vector sizes.
+# CHECK: SigInputVectors: 3
+# CHECK-NEXT: SigOutputVectors: [ 1, 1, 0, 0 ]
+
+# Verify the vector mask encodings.
+# CHECK: OutputVectorMasks:
+# CHECK-NEXT:   - [ 0xE ]
+# CHECK-NEXT:   - [ 0x5 ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [ 0x2, 0x4, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+# CHECK-NEXT:   - [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0x4, 0x8 ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
diff --git a/llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml b/llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml
new file mode 100644
index 0000000..0eaa2f8
--- /dev/null
+++ b/llvm/test/ObjectYAML/DXContainer/HullMaskVectors.yaml
@@ -0,0 +1,181 @@
+# RUN: yaml2obj %s | obj2yaml | FileCheck %s
+--- !dxcontainer
+Header:
+  Hash:            [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
+                     0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
+  Version:
+    Major:           1
+    Minor:           0
+  FileSize:        4612
+  PartCount:       8
+  PartOffsets:     [ 64, 80, 148, 208, 488, 740, 2468, 2496 ]
+Parts:
+  - Name:            SFI0
+    Size:            8
+    Flags:
+      Doubles:         false
+      ComputeShadersPlusRawAndStructuredBuffers: false
+      UAVsAtEveryStage: false
+      Max64UAVs:       false
+      MinimumPrecision: false
+      DX11_1_DoubleExtensions: false
+      DX11_1_ShaderExtensions: false
+      LEVEL9ComparisonFiltering: false
+      TiledResources:  false
+      StencilRef:      false
+      InnerCoverage:   false
+      TypedUAVLoadAdditionalFormats: false
+      ROVs:            false
+      ViewportAndRTArrayIndexFromAnyShaderFeedingRasterizer: false
+      WaveOps:         false
+      Int64Ops:        false
+      ViewID:          true
+      Barycentrics:    false
+      NativeLowPrecision: false
+      ShadingRate:     false
+      Raytracing_Tier_1_1: false
+      SamplerFeedback: false
+      AtomicInt64OnTypedResource: false
+      AtomicInt64OnGroupShared: false
+      DerivativesInMeshAndAmpShaders: false
+      ResourceDescriptorHeapIndexing: false
+      SamplerDescriptorHeapIndexing: false
+      RESERVED:        false
+      AtomicInt64OnHeapResource: false
+      AdvancedTextureOps: false
+      WriteableMSAATextures: false
+      NextUnusedBit:   false
+  - Name:            ISG1
+    Size:            60
+  - Name:            OSG1
+    Size:            52
+  - Name:            PSG1
+    Size:            272
+  - Name:            PSV0
+    Size:            244
+    PSVInfo:
+      Version:         2
+      ShaderStage:     3
+      InputControlPointCount: 32
+      OutputControlPointCount: 16
+      TessellatorDomain: 3
+      TessellatorOutputPrimitive: 3
+      MinimumWaveLaneCount: 0
+      MaximumWaveLaneCount: 4294967295
+      UsesViewID:      1
+      SigPatchConstOrPrimVectors: 7
+      SigInputVectors: 1
+      SigOutputVectors: [ 1, 0, 0, 0 ]
+      NumThreadsX:     0
+      NumThreadsY:     0
+      NumThreadsZ:     0
+      ResourceStride:  24
+      Resources:       []
+      SigInputElements:
+        - Name:            Sem_HSFoo_Input_qq
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          0
+      SigOutputElements:
+        - Name:            Sem_HSFoo
+          Indices:         [ 0 ]
+          StartRow:        0
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Linear
+          DynamicMask:     0x0
+          Stream:          0
+      SigPatchOrPrimElements:
+        - Name:            ''
+          Indices:         [ 0, 1, 2, 3 ]
+          StartRow:        0
+          Cols:            1
+          StartCol:        3
+          Allocated:       true
+          Kind:            TessFactor
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            ''
+          Indices:         [ 0, 1 ]
+          StartRow:        4
+          Cols:            1
+          StartCol:        3
+          Allocated:       true
+          Kind:            InsideTessFactor
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+        - Name:            AAA
+          Indices:         [ 0 ]
+          StartRow:        6
+          Cols:            4
+          StartCol:        0
+          Allocated:       true
+          Kind:            Arbitrary
+          ComponentType:   Float32
+          Interpolation:   Undefined
+          DynamicMask:     0x0
+          Stream:          0
+      OutputVectorMasks:
+        - [ 0x4 ]
+        - [  ]
+        - [  ]
+        - [  ]
+      PatchOrPrimMasks: [ 0x800080 ]
+      InputOutputMap:
+        - [ 0x5, 0x2, 0x4, 0xC ]
+        - [  ]
+        - [  ]
+        - [  ]
+      InputPatchMap:   [ 0x880000, 0x8888, 0x800000, 0x880000 ]
+  - Name:            STAT
+    Size:            1720
+  - Name:            HASH
+    Size:            20
+    Hash:
+      IncludesSource:  false
+      Digest:          [ 0xF4, 0x87, 0x4C, 0x40, 0xFD, 0x7A, 0x89, 0xFE, 
+                         0x1F, 0xC3, 0xAB, 0x8C, 0xC7, 0x18, 0xA9, 0xA ]
+  - Name:            DXIL
+    Size:            24
+    Program:
+      MajorVersion:    6
+      MinorVersion:    1
+      ShaderKind:      3
+      Size:            5627
+      DXILMajorVersion: 1
+      DXILMinorVersion: 1
+      DXILSize:        0
+...
+
+# Verify the vector sizes and ViewID use.
+# CHECK: UsesViewID:      1
+# CHECK-NEXT: SigPatchConstOrPrimVectors: 7
+# CHECK-NEXT: SigInputVectors: 1
+# CHECK-NEXT: SigOutputVectors: [ 1, 0, 0, 0 ]
+
+# Verify the vector encodings.
+# CHECK: OutputVectorMasks:
+# CHECK-NEXT:   - [ 0x4 ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: PatchOrPrimMasks: [ 0x800080 ]
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [ 0x5, 0x2, 0x4, 0xC ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
index 29e4b24..9822355 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
@@ -17,8 +17,8 @@ Parts:
       PayloadSizeInBytes: 4092
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -33,6 +33,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -52,8 +57,8 @@ Parts:
 # CHECK-NEXT: PayloadSizeInBytes: 4092
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
@@ -68,4 +73,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
index 8caae8c..629d45c 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
@@ -16,8 +16,8 @@ Parts:
       ShaderStage:     5
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -32,6 +32,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -50,8 +55,8 @@ Parts:
 # CHECK-NEXT: ShaderStage:     5
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
@@ -66,4 +71,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
index 8c7daa3..941ec16 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
@@ -19,10 +19,10 @@ Parts:
       TessellatorDomain: 2056
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigPatchConstOrPrimVectors:  128
-      SigInputVectors: 64
-      SigOutputVectors: [ 8, 16, 32, 64 ]
+      UsesViewID:      0
+      SigPatchConstOrPrimVectors:  0
+      SigInputVectors: 0
+      SigOutputVectors: [ 0, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
         - Type:            1
@@ -36,6 +36,12 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
+      PatchOutputMap: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -57,10 +63,10 @@ Parts:
 # CHECK-NEXT: TessellatorDomain: 2056
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigPatchConstOrPrimVectors:  128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigPatchConstOrPrimVectors:  0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
 # CHECK-NEXT: - Type:            1
@@ -74,4 +80,10 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: PatchOutputMap: [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
index 38f2a4c..a666cc4 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
@@ -20,9 +20,9 @@ Parts:
       OutputPositionPresent: 1
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
+      UsesViewID:      0
       MaxVertexCount:  4096
-      SigInputVectors: 64
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -37,6 +37,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -59,9 +64,9 @@ Parts:
 # CHECK-NEXT: OutputPositionPresent: 1
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: UsesViewID:      0
 # CHECK-NEXT: MaxVertexCount:  4096
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
@@ -76,4 +81,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
index 102907d..c0f0f41 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
@@ -20,10 +20,10 @@ Parts:
       TessellatorOutputPrimitive: 8192
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigPatchConstOrPrimVectors:  128
-      SigInputVectors: 64
-      SigOutputVectors: [ 8, 16, 32, 64 ]
+      UsesViewID:      0
+      SigPatchConstOrPrimVectors:  0
+      SigInputVectors: 0
+      SigOutputVectors: [ 0, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
         - Type:            1
@@ -37,6 +37,12 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
+      InputPatchMap: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -59,10 +65,10 @@ Parts:
 # CHECK-NEXT: TessellatorOutputPrimitive: 8192
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigPatchConstOrPrimVectors:  128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigPatchConstOrPrimVectors:  0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
 # CHECK-NEXT: - Type:            1
@@ -76,4 +82,10 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: InputPatchMap: [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
index 2bf8a3d..f981cb9 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
@@ -21,10 +21,10 @@ Parts:
       MaxOutputPrimitives: 4092
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
+      UsesViewID:      0
       SigPrimVectors:  128
       MeshOutputTopology: 16
-      SigInputVectors: 64
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -39,6 +39,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -62,10 +67,10 @@ Parts:
 # CHECK-NEXT: MaxOutputPrimitives: 4092
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: UsesViewID:      0
 # CHECK-NEXT: SigPrimVectors:  128
 # CHECK-NEXT: MeshOutputTopology: 16
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
@@ -80,4 +85,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
index df4ef44..a7b6804 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
@@ -18,8 +18,8 @@ Parts:
       SampleFrequency: 96
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -34,6 +34,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -54,8 +59,8 @@ Parts:
 # CHECK-NEXT: SampleFrequency: 96
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
@@ -70,4 +75,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
index 5bd8739..a9590ba 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
@@ -17,8 +17,8 @@ Parts:
       OutputPositionPresent: 1
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -33,6 +33,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -52,8 +57,8 @@ Parts:
 # CHECK-NEXT: OutputPositionPresent: 1
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
 # CHECK-NEXT: Resources:
@@ -68,4 +73,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
index 48f5edf..c1ad560 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
@@ -17,8 +17,8 @@ Parts:
       PayloadSizeInBytes: 4092
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
@@ -40,6 +40,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -59,8 +64,8 @@ Parts:
 # CHECK-NEXT: PayloadSizeInBytes: 4092
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
@@ -82,4 +87,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
index 16336f1..dc0ac3a 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
@@ -16,8 +16,8 @@ Parts:
       ShaderStage:     5
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
@@ -39,6 +39,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -57,8 +62,8 @@ Parts:
 # CHECK-NEXT: ShaderStage:     5
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
@@ -80,4 +85,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
index 4aab33a..03e23b0 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
@@ -19,10 +19,10 @@ Parts:
       TessellatorDomain: 2056
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigPatchConstOrPrimVectors:  128
-      SigInputVectors: 64
-      SigOutputVectors: [ 8, 16, 32, 64 ]
+      UsesViewID:      0
+      SigPatchConstOrPrimVectors:  0
+      SigInputVectors: 0
+      SigOutputVectors: [ 0, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
       NumThreadsZ:     2048
@@ -43,6 +43,12 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
+      PatchOutputMap: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -64,10 +70,10 @@ Parts:
 # CHECK-NEXT: TessellatorDomain: 2056
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigPatchConstOrPrimVectors:  128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigPatchConstOrPrimVectors:  0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
 # CHECK-NEXT: NumThreadsZ:     2048
@@ -88,4 +94,10 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: PatchOutputMap: [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
index 7fe7b84..b4a5efd 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
@@ -20,9 +20,9 @@ Parts:
       OutputPositionPresent: 1
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
+      UsesViewID:      0
       MaxVertexCount:  4096
-      SigInputVectors: 64
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
@@ -44,6 +44,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -66,9 +71,9 @@ Parts:
 # CHECK-NEXT: OutputPositionPresent: 1
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: UsesViewID:      0
 # CHECK-NEXT: MaxVertexCount:  4096
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
@@ -90,4 +95,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
index 4eb0dfc..a1c87343 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
@@ -20,10 +20,10 @@ Parts:
       TessellatorOutputPrimitive: 8192
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigPatchConstOrPrimVectors:  128
-      SigInputVectors: 64
-      SigOutputVectors: [ 8, 16, 32, 64 ]
+      UsesViewID:      0
+      SigPatchConstOrPrimVectors:  0
+      SigInputVectors: 0
+      SigOutputVectors: [ 0, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
       NumThreadsZ:     2048
@@ -44,6 +44,12 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
+      InputPatchMap: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -66,10 +72,10 @@ Parts:
 # CHECK-NEXT: TessellatorOutputPrimitive: 8192
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigPatchConstOrPrimVectors:  128
-# CHECK-NEXT: SigInputVectors: 64
-# CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigPatchConstOrPrimVectors:  0
+# CHECK-NEXT: SigInputVectors: 0
+# CHECK-NEXT: SigOutputVectors: [ 0, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
 # CHECK-NEXT: NumThreadsZ:     2048
@@ -90,4 +96,10 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT: InputPatchMap: [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
index 873acba..6155a3e 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
@@ -21,10 +21,10 @@ Parts:
       MaxOutputPrimitives: 4092
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
+      UsesViewID:      0
       SigPrimVectors:  128
       MeshOutputTopology: 16
-      SigInputVectors: 64
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
@@ -46,6 +46,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -69,10 +74,10 @@ Parts:
 # CHECK-NEXT: MaxOutputPrimitives: 4092
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: UsesViewID:      0
 # CHECK-NEXT: SigPrimVectors:  128
 # CHECK-NEXT: MeshOutputTopology: 16
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
@@ -94,4 +99,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
index 63e2de6..3fdd7be 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
@@ -18,8 +18,8 @@ Parts:
       SampleFrequency: 96
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
@@ -41,6 +41,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -61,8 +66,8 @@ Parts:
 # CHECK-NEXT: SampleFrequency: 96
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
@@ -84,4 +89,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
index fb595b5..eb77fb1 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
@@ -17,8 +17,8 @@ Parts:
       OutputPositionPresent: 1
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
       NumThreadsY:     1024
@@ -40,6 +40,11 @@ Parts:
       SigInputElements: []
       SigOutputElements: []
       SigPatchOrPrimElements: []
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program:
@@ -59,8 +64,8 @@ Parts:
 # CHECK-NEXT: OutputPositionPresent: 1
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
-# CHECK-NEXT: UsesViewID:      128
-# CHECK-NEXT: SigInputVectors: 64
+# CHECK-NEXT: UsesViewID:      0
+# CHECK-NEXT: SigInputVectors: 0
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
 # CHECK-NEXT: NumThreadsY:     1024
@@ -82,4 +87,9 @@ Parts:
 # CHECK-NEXT: SigInputElements: []
 # CHECK-NEXT: SigOutputElements: []
 # CHECK-NEXT: SigPatchOrPrimElements: []
+# CHECK-NEXT: InputOutputMap:
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
+# CHECK-NEXT:   - [  ]
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
index 8e2e5aa..47a18a6 100644
--- a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
@@ -18,8 +18,8 @@ Parts:
       SampleFrequency: 96
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
+      UsesViewID:      0
+      SigInputVectors: 0
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
       Resources:
@@ -78,6 +78,11 @@ Parts:
           Interpolation:   LinearSample
           DynamicMask:     0x2
           Stream:          3
+      InputOutputMap:
+        - [  ]
+        - [  ]
+        - [  ]
+        - [  ]
   - Name:            DXIL
     Size:            24
     Program: