Revert "[DX] Add support for PSV signature elements"

This reverts commit 8c567e64f808f7a818965c6bc123fedf7db7336f.

17 files changed, 96 insertions, 240 deletions

diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
index 29e4b24..94c215c 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
@@ -18,6 +18,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -30,9 +33,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -53,6 +53,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -65,7 +68,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
index 8caae8c..715b28b 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
@@ -17,6 +17,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -29,9 +32,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -51,6 +51,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -63,7 +66,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
index 8c7daa3..472b5e0 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
@@ -21,6 +21,9 @@ Parts:
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
       SigPatchConstOrPrimVectors:  128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -33,9 +36,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -59,6 +59,9 @@ Parts:
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: SigPatchConstOrPrimVectors:  128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -71,7 +74,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
index 38f2a4c..0c0a4ed 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
@@ -22,6 +22,9 @@ Parts:
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
       MaxVertexCount:  4096
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -34,9 +37,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -61,6 +61,9 @@ Parts:
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: MaxVertexCount:  4096
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -73,7 +76,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
index 102907d..330d24f 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml
@@ -22,6 +22,9 @@ Parts:
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
       SigPatchConstOrPrimVectors:  128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -34,9 +37,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -61,6 +61,9 @@ Parts:
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: SigPatchConstOrPrimVectors:  128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -73,7 +76,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
index 2bf8a3d..51bd639 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml
@@ -24,6 +24,9 @@ Parts:
       UsesViewID:      128
       SigPrimVectors:  128
       MeshOutputTopology: 16
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -36,9 +39,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -65,6 +65,9 @@ Parts:
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: SigPrimVectors:  128
 # CHECK-NEXT: MeshOutputTopology: 16
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -77,7 +80,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
index df4ef44..2e49034 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml
@@ -19,6 +19,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -31,9 +34,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -55,6 +55,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -67,7 +70,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
index 5bd8739..ad8f082 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
@@ -18,6 +18,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       ResourceStride:       16
@@ -30,9 +33,6 @@ Parts:
           Space:           32768
           LowerBound:      8388608
           UpperBound:      2147483648
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -53,6 +53,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: ResourceStride: 16
@@ -65,7 +68,4 @@ Parts:
 # CHECK-NEXT: Space:           32768
 # CHECK-NEXT: LowerBound:      8388608
 # CHECK-NEXT: UpperBound:      2147483648
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
index 48f5edf..d4fee91 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
@@ -18,6 +18,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -37,9 +40,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -60,6 +60,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -79,7 +82,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
index 16336f1..5ee136b 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
@@ -17,6 +17,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -36,9 +39,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -58,6 +58,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -77,7 +80,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
index 4aab33a..4ed9f04 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
@@ -21,6 +21,9 @@ Parts:
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
       SigPatchConstOrPrimVectors:  128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -40,9 +43,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -66,6 +66,9 @@ Parts:
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: SigPatchConstOrPrimVectors:  128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -85,7 +88,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
index 7fe7b84..66def9b 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
@@ -22,6 +22,9 @@ Parts:
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
       MaxVertexCount:  4096
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -41,9 +44,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -68,6 +68,9 @@ Parts:
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: MaxVertexCount:  4096
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -87,7 +90,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
index 4eb0dfc..0a35992 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml
@@ -22,6 +22,9 @@ Parts:
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
       SigPatchConstOrPrimVectors:  128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -41,9 +44,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -68,6 +68,9 @@ Parts:
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: SigPatchConstOrPrimVectors:  128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -87,7 +90,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
index 873acba..ec81b60 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml
@@ -24,6 +24,9 @@ Parts:
       UsesViewID:      128
       SigPrimVectors:  128
       MeshOutputTopology: 16
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -43,9 +46,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -72,6 +72,9 @@ Parts:
 # CHECK-NEXT: UsesViewID:      128
 # CHECK-NEXT: SigPrimVectors:  128
 # CHECK-NEXT: MeshOutputTopology: 16
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -91,7 +94,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
index 63e2de6..60e53f8 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml
@@ -19,6 +19,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -38,9 +41,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -62,6 +62,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -81,7 +84,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
index fb595b5..15b227c 100644
--- a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
+++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
@@ -18,6 +18,9 @@ Parts:
       MinimumWaveLaneCount: 0
       MaximumWaveLaneCount: 4294967295
       UsesViewID:      128
+      SigInputElements: 8
+      SigOutputElements: 16
+      SigPatchConstOrPrimElements: 32
       SigInputVectors: 64
       SigOutputVectors: [ 8, 16, 32, 64 ]
       NumThreadsX:     512
@@ -37,9 +40,6 @@ Parts:
           UpperBound:      2147483648
           Kind:            65535
           Flags:           16776960
-      SigInputElements: []
-      SigOutputElements: []
-      SigPatchOrPrimElements: []
   - Name:            DXIL
     Size:            24
     Program:
@@ -60,6 +60,9 @@ Parts:
 # CHECK-NEXT: MinimumWaveLaneCount: 0
 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295
 # CHECK-NEXT: UsesViewID:      128
+# CHECK-NEXT: SigInputElements: 8
+# CHECK-NEXT: SigOutputElements: 16
+# CHECK-NEXT: SigPatchConstOrPrimElements: 32
 # CHECK-NEXT: SigInputVectors: 64
 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ]
 # CHECK-NEXT: NumThreadsX:     512
@@ -79,7 +82,4 @@ Parts:
 # CHECK-NEXT: UpperBound:      2147483648
 # CHECK-NEXT: Kind:            65535
 # CHECK-NEXT: Flags:           16776960
-# CHECK-NEXT: SigInputElements: []
-# CHECK-NEXT: SigOutputElements: []
-# CHECK-NEXT: SigPatchOrPrimElements: []
 # CHECK-NEXT: Name
diff --git a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
deleted file mode 100644
index 8e2e5aa..0000000
--- a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml
+++ /dev/null
@@ -1,144 +0,0 @@
-# RUN: yaml2obj %s | obj2yaml | FileCheck %s
-
---- !dxcontainer
-Header:
-  Hash:            [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
-                     0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ]
-  Version:
-    Major:           1
-    Minor:           0
-  PartCount:       2
-Parts:
-  - Name:            PSV0
-    Size:            250
-    PSVInfo:
-      Version:         1
-      ShaderStage:     0
-      DepthOutput:     7
-      SampleFrequency: 96
-      MinimumWaveLaneCount: 0
-      MaximumWaveLaneCount: 4294967295
-      UsesViewID:      128
-      SigInputVectors: 64
-      SigOutputVectors: [ 8, 16, 32, 64 ]
-      ResourceStride:       16
-      Resources:
-        - Type:            1
-          Space:           2
-          LowerBound:      3
-          UpperBound:      4
-        - Type:            128
-          Space:           32768
-          LowerBound:      8388608
-          UpperBound:      2147483648
-      SigInputElements:
-        - Name:            IN
-          Indices:         [ 0, 1 ]
-          StartRow:        0
-          Cols:            2
-          StartCol:        0
-          Allocated:       true
-          Kind:            Arbitrary
-          ComponentType:   SInt32
-          Interpolation:   Undefined
-          DynamicMask:     0x0
-          Stream:          0
-      SigOutputElements:
-        - Name:            OUT
-          Indices:         [ 0, 1 ]
-          StartRow:        0
-          Cols:            2
-          StartCol:        0
-          Allocated:       true
-          Kind:            Arbitrary
-          ComponentType:   Float32
-          Interpolation:   Linear
-          DynamicMask:     0x0
-          Stream:          1
-      SigPatchOrPrimElements:
-        - Name:            Patch
-          Indices:         [ 0 ]
-          StartRow:        0
-          Cols:            1
-          StartCol:        0
-          Allocated:       true
-          Kind:            Arbitrary
-          ComponentType:   Float32
-          Interpolation:   Linear
-          DynamicMask:     0x1
-          Stream:          2
-        - Name:            Patch1
-          Indices:         [ 2 ]
-          StartRow:        0
-          Cols:            1
-          StartCol:        0
-          Allocated:       true
-          Kind:            Arbitrary
-          ComponentType:   Float64
-          Interpolation:   LinearSample
-          DynamicMask:     0x2
-          Stream:          3
-  - Name:            DXIL
-    Size:            24
-    Program:
-      MajorVersion:    6
-      MinorVersion:    0
-      ShaderKind:      0
-      Size:            6
-      DXILMajorVersion: 0
-      DXILMinorVersion: 1
-      DXILSize:        0
-...
-
-# CHECK: Name:            PSV0
-# CHECK: PSVInfo:
-# CHECK-NEXT: Version:         1
-# CHECK-NEXT: ShaderStage:     0
-
-# CHECK: SigInputElements:
-# CHECK-NEXT:   - Name:            IN
-# CHECK-NEXT:     Indices:         [ 0, 1 ]
-# CHECK-NEXT:     StartRow:        0
-# CHECK-NEXT:     Cols:            2
-# CHECK-NEXT:     StartCol:        0
-# CHECK-NEXT:     Allocated:       true
-# CHECK-NEXT:     Kind:            Arbitrary
-# CHECK-NEXT:     ComponentType:   SInt32
-# CHECK-NEXT:     Interpolation:   Undefined
-# CHECK-NEXT:     DynamicMask:     0x0
-# CHECK-NEXT:     Stream:          0
-# CHECK-NEXT: SigOutputElements:
-# CHECK-NEXT:   - Name:            OUT
-# CHECK-NEXT:     Indices:         [ 0, 1 ]
-# CHECK-NEXT:     StartRow:        0
-# CHECK-NEXT:     Cols:            2
-# CHECK-NEXT:     StartCol:        0
-# CHECK-NEXT:     Allocated:       true
-# CHECK-NEXT:     Kind:            Arbitrary
-# CHECK-NEXT:     ComponentType:   Float32
-# CHECK-NEXT:     Interpolation:   Linear
-# CHECK-NEXT:     DynamicMask:     0x0
-# CHECK-NEXT:     Stream:          1
-# CHECK-NEXT: SigPatchOrPrimElements:
-# CHECK-NEXT:   - Name:            Patch
-# CHECK-NEXT:     Indices:         [ 0 ]
-# CHECK-NEXT:     StartRow:        0
-# CHECK-NEXT:     Cols:            1
-# CHECK-NEXT:     StartCol:        0
-# CHECK-NEXT:     Allocated:       true
-# CHECK-NEXT:     Kind:            Arbitrary
-# CHECK-NEXT:     ComponentType:   Float32
-# CHECK-NEXT:     Interpolation:   Linear
-# CHECK-NEXT:     DynamicMask:     0x1
-# CHECK-NEXT:     Stream:          2
-# CHECK-NEXT:   - Name:            Patch1
-# CHECK-NEXT:     Indices:         [ 2 ]
-# CHECK-NEXT:     StartRow:        0
-# CHECK-NEXT:     Cols:            1
-# CHECK-NEXT:     StartCol:        0
-# CHECK-NEXT:     Allocated:       true
-# CHECK-NEXT:     Kind:            Arbitrary
-# CHECK-NEXT:     ComponentType:   Float64
-# CHECK-NEXT:     Interpolation:   LinearSample
-# CHECK-NEXT:     DynamicMask:     0x2
-# CHECK-NEXT:     Stream:          3