diff options
author | Chris Bieneman <chris.bieneman@me.com> | 2023-08-10 20:26:19 -0500 |
---|---|---|
committer | Chris Bieneman <chris.bieneman@me.com> | 2023-08-16 14:26:13 -0500 |
commit | 0c3f51c0427022f16129a6ac4d2a11ad83ae7703 (patch) | |
tree | b4046a3fa1588fd5baa85a80bde856570e6777ef /llvm/test/ObjectYAML | |
parent | d268ba38083cd7c9c4f55cb0792d4a0db1d4768b (diff) | |
download | llvm-0c3f51c0427022f16129a6ac4d2a11ad83ae7703.zip llvm-0c3f51c0427022f16129a6ac4d2a11ad83ae7703.tar.gz llvm-0c3f51c0427022f16129a6ac4d2a11ad83ae7703.tar.bz2 |
Re-land [DX] Add support for PSV signature elements
The pipeline state data captured in the PSV0 section of the DXContainer
file encodes signature elements which are read by the runtime to map
inputs and outputs from the GPU program.
This change adds support for generating and parsing signature elements
with testing driven through the ObjectYAML tooling.
Reviewed By: bogner
Differential Revision: https://reviews.llvm.org/D157671
Initially landed as 8c567e64f808f7a818965c6bc123fedf7db7336f, and
reverted in 4d800633b2683304a5431d002d8ffc40a1815520.
../llvm/include/llvm/BinaryFormat/DXContainerConstants.def
../llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml
../llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml
Diffstat (limited to 'llvm/test/ObjectYAML')
17 files changed, 240 insertions, 96 deletions
diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml index 94c215c..29e4b24 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-amplification.yaml @@ -18,9 +18,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -33,6 +30,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -53,9 +53,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -68,4 +65,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml index 715b28b..8caae8c 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-compute.yaml @@ -17,9 +17,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -32,6 +29,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -51,9 +51,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -66,4 +63,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml index 472b5e0..8c7daa3 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-domain.yaml @@ -21,9 +21,6 @@ Parts: MaximumWaveLaneCount: 4294967295 UsesViewID: 128 SigPatchConstOrPrimVectors: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -36,6 +33,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -59,9 +59,6 @@ Parts: # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: SigPatchConstOrPrimVectors: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -74,4 +71,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml index 0c0a4ed..38f2a4c 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-geometry.yaml @@ -22,9 +22,6 @@ Parts: MaximumWaveLaneCount: 4294967295 UsesViewID: 128 MaxVertexCount: 4096 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -37,6 +34,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -61,9 +61,6 @@ Parts: # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: MaxVertexCount: 4096 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -76,4 +73,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml index 330d24f..102907d 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-hull.yaml @@ -22,9 +22,6 @@ Parts: MaximumWaveLaneCount: 4294967295 UsesViewID: 128 SigPatchConstOrPrimVectors: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -37,6 +34,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -61,9 +61,6 @@ Parts: # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: SigPatchConstOrPrimVectors: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -76,4 +73,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml index 51bd639..2bf8a3d 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-mesh.yaml @@ -24,9 +24,6 @@ Parts: UsesViewID: 128 SigPrimVectors: 128 MeshOutputTopology: 16 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -39,6 +36,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -65,9 +65,6 @@ Parts: # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: SigPrimVectors: 128 # CHECK-NEXT: MeshOutputTopology: 16 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -80,4 +77,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml index 2e49034..df4ef44 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-pixel.yaml @@ -19,9 +19,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -34,6 +31,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -55,9 +55,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -70,4 +67,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml index ad8f082..5bd8739 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv1-vertex.yaml @@ -18,9 +18,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] ResourceStride: 16 @@ -33,6 +30,9 @@ Parts: Space: 32768 LowerBound: 8388608 UpperBound: 2147483648 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -53,9 +53,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: ResourceStride: 16 @@ -68,4 +65,7 @@ Parts: # CHECK-NEXT: Space: 32768 # CHECK-NEXT: LowerBound: 8388608 # CHECK-NEXT: UpperBound: 2147483648 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml index d4fee91..48f5edf 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-amplification.yaml @@ -18,9 +18,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -40,6 +37,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -60,9 +60,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -82,4 +79,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml index 5ee136b..16336f1 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-compute.yaml @@ -17,9 +17,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -39,6 +36,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -58,9 +58,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -80,4 +77,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml index 4ed9f04..4aab33a 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-domain.yaml @@ -21,9 +21,6 @@ Parts: MaximumWaveLaneCount: 4294967295 UsesViewID: 128 SigPatchConstOrPrimVectors: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -43,6 +40,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -66,9 +66,6 @@ Parts: # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: SigPatchConstOrPrimVectors: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -88,4 +85,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml index 66def9b..7fe7b84 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-geometry.yaml @@ -22,9 +22,6 @@ Parts: MaximumWaveLaneCount: 4294967295 UsesViewID: 128 MaxVertexCount: 4096 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -44,6 +41,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -68,9 +68,6 @@ Parts: # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: MaxVertexCount: 4096 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -90,4 +87,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml index 0a35992..4eb0dfc 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-hull.yaml @@ -22,9 +22,6 @@ Parts: MaximumWaveLaneCount: 4294967295 UsesViewID: 128 SigPatchConstOrPrimVectors: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -44,6 +41,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -68,9 +68,6 @@ Parts: # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: SigPatchConstOrPrimVectors: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -90,4 +87,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml index ec81b60..873acba 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-mesh.yaml @@ -24,9 +24,6 @@ Parts: UsesViewID: 128 SigPrimVectors: 128 MeshOutputTopology: 16 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -46,6 +43,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -72,9 +72,6 @@ Parts: # CHECK-NEXT: UsesViewID: 128 # CHECK-NEXT: SigPrimVectors: 128 # CHECK-NEXT: MeshOutputTopology: 16 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -94,4 +91,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml index 60e53f8..63e2de6 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-pixel.yaml @@ -19,9 +19,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -41,6 +38,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -62,9 +62,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -84,4 +81,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml index 15b227c..fb595b5 100644 --- a/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml +++ b/llvm/test/ObjectYAML/DXContainer/PSVv2-vertex.yaml @@ -18,9 +18,6 @@ Parts: MinimumWaveLaneCount: 0 MaximumWaveLaneCount: 4294967295 UsesViewID: 128 - SigInputElements: 8 - SigOutputElements: 16 - SigPatchConstOrPrimElements: 32 SigInputVectors: 64 SigOutputVectors: [ 8, 16, 32, 64 ] NumThreadsX: 512 @@ -40,6 +37,9 @@ Parts: UpperBound: 2147483648 Kind: 65535 Flags: 16776960 + SigInputElements: [] + SigOutputElements: [] + SigPatchOrPrimElements: [] - Name: DXIL Size: 24 Program: @@ -60,9 +60,6 @@ Parts: # CHECK-NEXT: MinimumWaveLaneCount: 0 # CHECK-NEXT: MaximumWaveLaneCount: 4294967295 # CHECK-NEXT: UsesViewID: 128 -# CHECK-NEXT: SigInputElements: 8 -# CHECK-NEXT: SigOutputElements: 16 -# CHECK-NEXT: SigPatchConstOrPrimElements: 32 # CHECK-NEXT: SigInputVectors: 64 # CHECK-NEXT: SigOutputVectors: [ 8, 16, 32, 64 ] # CHECK-NEXT: NumThreadsX: 512 @@ -82,4 +79,7 @@ Parts: # CHECK-NEXT: UpperBound: 2147483648 # CHECK-NEXT: Kind: 65535 # CHECK-NEXT: Flags: 16776960 +# CHECK-NEXT: SigInputElements: [] +# CHECK-NEXT: SigOutputElements: [] +# CHECK-NEXT: SigPatchOrPrimElements: [] # CHECK-NEXT: Name diff --git a/llvm/test/ObjectYAML/DXContainer/SigElements.yaml b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml new file mode 100644 index 0000000..8e2e5aa --- /dev/null +++ b/llvm/test/ObjectYAML/DXContainer/SigElements.yaml @@ -0,0 +1,144 @@ +# RUN: yaml2obj %s | obj2yaml | FileCheck %s + +--- !dxcontainer +Header: + Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] + Version: + Major: 1 + Minor: 0 + PartCount: 2 +Parts: + - Name: PSV0 + Size: 250 + PSVInfo: + Version: 1 + ShaderStage: 0 + DepthOutput: 7 + SampleFrequency: 96 + MinimumWaveLaneCount: 0 + MaximumWaveLaneCount: 4294967295 + UsesViewID: 128 + SigInputVectors: 64 + SigOutputVectors: [ 8, 16, 32, 64 ] + ResourceStride: 16 + Resources: + - Type: 1 + Space: 2 + LowerBound: 3 + UpperBound: 4 + - Type: 128 + Space: 32768 + LowerBound: 8388608 + UpperBound: 2147483648 + SigInputElements: + - Name: IN + Indices: [ 0, 1 ] + StartRow: 0 + Cols: 2 + StartCol: 0 + Allocated: true + Kind: Arbitrary + ComponentType: SInt32 + Interpolation: Undefined + DynamicMask: 0x0 + Stream: 0 + SigOutputElements: + - Name: OUT + Indices: [ 0, 1 ] + StartRow: 0 + Cols: 2 + StartCol: 0 + Allocated: true + Kind: Arbitrary + ComponentType: Float32 + Interpolation: Linear + DynamicMask: 0x0 + Stream: 1 + SigPatchOrPrimElements: + - Name: Patch + Indices: [ 0 ] + StartRow: 0 + Cols: 1 + StartCol: 0 + Allocated: true + Kind: Arbitrary + ComponentType: Float32 + Interpolation: Linear + DynamicMask: 0x1 + Stream: 2 + - Name: Patch1 + Indices: [ 2 ] + StartRow: 0 + Cols: 1 + StartCol: 0 + Allocated: true + Kind: Arbitrary + ComponentType: Float64 + Interpolation: LinearSample + DynamicMask: 0x2 + Stream: 3 + - Name: DXIL + Size: 24 + Program: + MajorVersion: 6 + MinorVersion: 0 + ShaderKind: 0 + Size: 6 + DXILMajorVersion: 0 + DXILMinorVersion: 1 + DXILSize: 0 +... + +# CHECK: Name: PSV0 +# CHECK: PSVInfo: +# CHECK-NEXT: Version: 1 +# CHECK-NEXT: ShaderStage: 0 + +# CHECK: SigInputElements: +# CHECK-NEXT: - Name: IN +# CHECK-NEXT: Indices: [ 0, 1 ] +# CHECK-NEXT: StartRow: 0 +# CHECK-NEXT: Cols: 2 +# CHECK-NEXT: StartCol: 0 +# CHECK-NEXT: Allocated: true +# CHECK-NEXT: Kind: Arbitrary +# CHECK-NEXT: ComponentType: SInt32 +# CHECK-NEXT: Interpolation: Undefined +# CHECK-NEXT: DynamicMask: 0x0 +# CHECK-NEXT: Stream: 0 +# CHECK-NEXT: SigOutputElements: +# CHECK-NEXT: - Name: OUT +# CHECK-NEXT: Indices: [ 0, 1 ] +# CHECK-NEXT: StartRow: 0 +# CHECK-NEXT: Cols: 2 +# CHECK-NEXT: StartCol: 0 +# CHECK-NEXT: Allocated: true +# CHECK-NEXT: Kind: Arbitrary +# CHECK-NEXT: ComponentType: Float32 +# CHECK-NEXT: Interpolation: Linear +# CHECK-NEXT: DynamicMask: 0x0 +# CHECK-NEXT: Stream: 1 +# CHECK-NEXT: SigPatchOrPrimElements: +# CHECK-NEXT: - Name: Patch +# CHECK-NEXT: Indices: [ 0 ] +# CHECK-NEXT: StartRow: 0 +# CHECK-NEXT: Cols: 1 +# CHECK-NEXT: StartCol: 0 +# CHECK-NEXT: Allocated: true +# CHECK-NEXT: Kind: Arbitrary +# CHECK-NEXT: ComponentType: Float32 +# CHECK-NEXT: Interpolation: Linear +# CHECK-NEXT: DynamicMask: 0x1 +# CHECK-NEXT: Stream: 2 +# CHECK-NEXT: - Name: Patch1 +# CHECK-NEXT: Indices: [ 2 ] +# CHECK-NEXT: StartRow: 0 +# CHECK-NEXT: Cols: 1 +# CHECK-NEXT: StartCol: 0 +# CHECK-NEXT: Allocated: true +# CHECK-NEXT: Kind: Arbitrary +# CHECK-NEXT: ComponentType: Float64 +# CHECK-NEXT: Interpolation: LinearSample +# CHECK-NEXT: DynamicMask: 0x2 +# CHECK-NEXT: Stream: 3 |