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| author | Jessica Paquette <jpaquette@apple.com> | 2021-08-17 09:45:23 -0700 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2021-08-18 10:42:05 -0700 |
| commit | 0a2b1ba33ae6dcaedb81417f7c4cc714f72a5968 (patch) | |
| tree | 4f37456dea2c6b7541bccec52ca994a839217aaf /llvm/test/MachineVerifier | |
| parent | e8c8407aca7c6c5778cb969fef89ffaa212d6de5 (diff) | |
| download | llvm-0a2b1ba33ae6dcaedb81417f7c4cc714f72a5968.zip llvm-0a2b1ba33ae6dcaedb81417f7c4cc714f72a5968.tar.gz llvm-0a2b1ba33ae6dcaedb81417f7c4cc714f72a5968.tar.bz2 | |
[GlobalISel] Add G_ISNAN
Add a generic opcode equivalent to the `llvm.isnan` intrinsic +
MachineVerifier support for it.
We need an opcode here because we may want target-specific lowering later on.
Differential Revision: https://reviews.llvm.org/D108222
Diffstat (limited to 'llvm/test/MachineVerifier')
| -rw-r--r-- | llvm/test/MachineVerifier/test_g_isnan.mir | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/MachineVerifier/test_g_isnan.mir b/llvm/test/MachineVerifier/test_g_isnan.mir new file mode 100644 index 0000000..94bc93b --- /dev/null +++ b/llvm/test/MachineVerifier/test_g_isnan.mir @@ -0,0 +1,33 @@ +# REQUIRES: aarch64-registered-target +# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s + +name: test +body: | + bb.0: + liveins: $x0 + %s64:_(s64) = COPY $x0 + %v4s16:_(<4 x s16>) = COPY $x0 + + ; CHECK: *** Bad machine code: Destination must be a 1-bit scalar or vector of 1-bit elements *** + ; CHECK: instruction: %isnan1:_(s64) = G_ISNAN %s64:_(s64) + %isnan1:_(s64) = G_ISNAN %s64 + + ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar *** + ; CHECK: instruction: %isnan2:_(<2 x s1>) = G_ISNAN %s64:_(s64) + %isnan2:_(<2 x s1>) = G_ISNAN %s64 + + ; CHECK: *** Bad machine code: operand types must preserve number of vector elements *** + ; CHECK: instruction: %isnan3:_(<2 x s1>) = G_ISNAN %v4s16:_(<4 x s16>) + %isnan3:_(<2 x s1>) = G_ISNAN %v4s16 + + ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar *** + ; CHECK: instruction: %isnan4:_(s1) = G_ISNAN %v4s16:_(<4 x s16>) + %isnan4:_(s1) = G_ISNAN %v4s16 + + ; CHECK: *** Bad machine code: Destination must be a 1-bit scalar or vector of 1-bit elements *** + ; CHECK: instruction: %isnan5:_(p0) = G_ISNAN %s64:_(s64) + %isnan5:_(p0) = G_ISNAN %s64 + + ; CHECK: *** Bad machine code: Destination must be a 1-bit scalar or vector of 1-bit elements *** + ; CHECK: instruction: %isnan6:_(<4 x p0>) = G_ISNAN %v4s16:_(<4 x s16>) + %isnan6:_(<4 x p0>) = G_ISNAN %v4s16 |