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author | Brendan Sweeney <brs@eecs.berkeley.edu> | 2024-02-01 12:58:21 -0600 |
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committer | GitHub <noreply@github.com> | 2024-02-01 10:58:21 -0800 |
commit | e296cedcd686e24fee75756185669f1bb3b47fdd (patch) | |
tree | ca51c2871298173392cfefd678800eea53fa2100 /llvm/test/MC | |
parent | ef7f6aca149c88089ec4964e87889f3709321f03 (diff) | |
download | llvm-e296cedcd686e24fee75756185669f1bb3b47fdd.zip llvm-e296cedcd686e24fee75756185669f1bb3b47fdd.tar.gz llvm-e296cedcd686e24fee75756185669f1bb3b47fdd.tar.bz2 |
[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
This PR implements experimental support for the RISC-V Atomic
Load-Acquire and Store-Release Extension (Zalasr). It has been approved
to be pursued as a fast track extension
(https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698),
but has not yet been approved by ARC or ratified. See
https://github.com/mehnadnerd/riscv-zalasr for draft spec.
---------
Co-authored-by: brs <turtwig@utexas.edu>
Co-authored-by: Philip Reames <preames@rivosinc.com>
Diffstat (limited to 'llvm/test/MC')
-rw-r--r-- | llvm/test/MC/RISCV/attribute-arch.s | 3 | ||||
-rw-r--r-- | llvm/test/MC/RISCV/rv32zalasr-invalid.s | 40 | ||||
-rw-r--r-- | llvm/test/MC/RISCV/rv32zalasr-valid.s | 78 | ||||
-rw-r--r-- | llvm/test/MC/RISCV/rv64zalasr-invalid.s | 28 | ||||
-rw-r--r-- | llvm/test/MC/RISCV/rv64zalasr-valid.s | 31 |
5 files changed, 180 insertions, 0 deletions
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 5f9a7ca..8810ca67 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -309,6 +309,9 @@ .attribute arch, "rv32izacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0" +.attribute arch, "rv32izalasr0p1" +# CHECK: attribute 5, "rv32i2p1_zalasr0p1" + .attribute arch, "rv32i_xcvalu" # CHECK: attribute 5, "rv32i2p1_xcvalu1p0" diff --git a/llvm/test/MC/RISCV/rv32zalasr-invalid.s b/llvm/test/MC/RISCV/rv32zalasr-invalid.s new file mode 100644 index 0000000..3731c85 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zalasr-invalid.s @@ -0,0 +1,40 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +ld.aq a1, (t0) + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +ld.aqrl a1, (t0) + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sd.rl a1, (t0) + +# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sd.aqrl a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +lw. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +lw.rl t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +lh.rlaq t4, (t6) + +# CHECK: error: unrecognized instruction mnemonic +sb. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +sh.aq t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +sh.rlaq t4, (t6) + +# CHECK: error: optional integer offset must be 0 +lw.aq zero, 1(a0) + +# CHECK: error: optional integer offset must be 0 +sw.rl t1, 2(s0) + +# CHECK: error: optional integer offset must be 0 +sb.aqrl sp, 3(s2) diff --git a/llvm/test/MC/RISCV/rv32zalasr-valid.s b/llvm/test/MC/RISCV/rv32zalasr-valid.s new file mode 100644 index 0000000..7b2668b --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zalasr-valid.s @@ -0,0 +1,78 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalasr < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv64 \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s + +# CHECK-ASM-AND-OBJ: lb.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lb.aq t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lh.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lh.aq t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lw.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lw.aq t1, (a0) + +# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lb.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lh.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +lw.aqrl t1, (a0) + + +# CHECK-ASM-AND-OBJ: sb.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sb.rl t1, (a0) + +# CHECK-ASM-AND-OBJ: sh.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sh.rl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sw.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sw.rl t1, (a0) + +# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sb.aqrl t1, (a0) + +# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sh.aqrl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sw.aqrl t1, 0(a0) diff --git a/llvm/test/MC/RISCV/rv64zalasr-invalid.s b/llvm/test/MC/RISCV/rv64zalasr-invalid.s new file mode 100644 index 0000000..032c0c00 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zalasr-invalid.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +# CHECK: error: unrecognized instruction mnemonic +lw. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +lw.rl t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +lh.rlaq t4, (t6) + +# CHECK: error: unrecognized instruction mnemonic +sb. a1, (t0) + +# CHECK: error: unrecognized instruction mnemonic +sh.aq t3, 0(t5) + +# CHECK: error: unrecognized instruction mnemonic +sh.rlaq t4, (t6) + +# CHECK: error: optional integer offset must be 0 +lw.aq zero, 1(a0) + +# CHECK: error: optional integer offset must be 0 +sw.rl t1, 2(s0) + +# CHECK: error: optional integer offset must be 0 +sb.aqrl sp, 3(s2) diff --git a/llvm/test/MC/RISCV/rv64zalasr-valid.s b/llvm/test/MC/RISCV/rv64zalasr-valid.s new file mode 100644 index 0000000..2f1e381 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zalasr-valid.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv64 \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s + + +# CHECK-ASM-AND-OBJ: ld.aq t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x34] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +ld.aq t1, (a0) + +# CHECK-ASM-AND-OBJ: ld.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x36] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +ld.aqrl t1, 0(a0) + + +# CHECK-ASM-AND-OBJ: sd.rl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3a] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sd.rl t1, 0(a0) + +# CHECK-ASM-AND-OBJ: sd.aqrl t1, (a0) +# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3e] +# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}} +sd.aqrl t1, (a0) |