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| author | Andrés Villegas <andresvi@google.com> | 2024-01-03 23:05:20 +0000 |
|---|---|---|
| committer | Andrés Villegas <andresvi@google.com> | 2024-01-03 23:05:20 +0000 |
| commit | e99fdd060baf7ea196f9b9e531b58e5d8489f5fd (patch) | |
| tree | 56305609013119524612245bd222dac094de4f68 /llvm/test/MC/RISCV/fixups-expr.s | |
| parent | d242f164d69ec606db9418c02c9588bffa429928 (diff) | |
| parent | 51113244836be55b3d2f181c0f88043b5967eb61 (diff) | |
| download | llvm-users/avillega/clangd-migrate-command-line-option-parsin-to-opttable.zip llvm-users/avillega/clangd-migrate-command-line-option-parsin-to-opttable.tar.gz llvm-users/avillega/clangd-migrate-command-line-option-parsin-to-opttable.tar.bz2 | |
Created using spr 1.3.5
Diffstat (limited to 'llvm/test/MC/RISCV/fixups-expr.s')
| -rw-r--r-- | llvm/test/MC/RISCV/fixups-expr.s | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/test/MC/RISCV/fixups-expr.s b/llvm/test/MC/RISCV/fixups-expr.s index 8a02d29..63e7f2e 100644 --- a/llvm/test/MC/RISCV/fixups-expr.s +++ b/llvm/test/MC/RISCV/fixups-expr.s @@ -16,11 +16,15 @@ .globl G1 .globl G2 +.globl G3 .L1: G1: call extern .L2: G2: + .p2align 3 +.L3: +G3: .data .dword .L2-.L1 @@ -31,6 +35,14 @@ G2: .half G2-G1 .byte .L2-.L1 .byte G2-G1 +.dword .L3-.L2 +.dword G3-G2 +.word .L3-.L2 +.word G3-G2 +.half .L3-.L2 +.half G3-G2 +.byte .L3-.L2 +.byte G3-G2 # RELAX: .rela.data { # RELAX-NEXT: 0x0 R_RISCV_ADD64 .L2 0x0 # RELAX-NEXT: 0x0 R_RISCV_SUB64 .L1 0x0 @@ -48,4 +60,20 @@ G2: # RELAX-NEXT: 0x1C R_RISCV_SUB8 .L1 0x0 # RELAX-NEXT: 0x1D R_RISCV_ADD8 G2 0x0 # RELAX-NEXT: 0x1D R_RISCV_SUB8 G1 0x0 +# RELAX-NEXT: 0x1E R_RISCV_ADD64 .L3 0x0 +# RELAX-NEXT: 0x1E R_RISCV_SUB64 .L2 0x0 +# RELAX-NEXT: 0x26 R_RISCV_ADD64 G3 0x0 +# RELAX-NEXT: 0x26 R_RISCV_SUB64 G2 0x0 +# RELAX-NEXT: 0x2E R_RISCV_ADD32 .L3 0x0 +# RELAX-NEXT: 0x2E R_RISCV_SUB32 .L2 0x0 +# RELAX-NEXT: 0x32 R_RISCV_ADD32 G3 0x0 +# RELAX-NEXT: 0x32 R_RISCV_SUB32 G2 0x0 +# RELAX-NEXT: 0x36 R_RISCV_ADD16 .L3 0x0 +# RELAX-NEXT: 0x36 R_RISCV_SUB16 .L2 0x0 +# RELAX-NEXT: 0x38 R_RISCV_ADD16 G3 0x0 +# RELAX-NEXT: 0x38 R_RISCV_SUB16 G2 0x0 +# RELAX-NEXT: 0x3A R_RISCV_ADD8 .L3 0x0 +# RELAX-NEXT: 0x3A R_RISCV_SUB8 .L2 0x0 +# RELAX-NEXT: 0x3B R_RISCV_ADD8 G3 0x0 +# RELAX-NEXT: 0x3B R_RISCV_SUB8 G2 0x0 # RELAX-NEXT: } |