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| author | Alex MacLean <amaclean@nvidia.com> | 2024-01-17 16:18:39 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-17 16:18:39 -0800 |
| commit | 430a40d12eaa5a61792c4670955c110146902afb (patch) | |
| tree | 33f82c05a67529ee9aa3efbad1d7d3b8aa610ba4 /llvm/test/CodeGen/X86/apx | |
| parent | f2b5a314b29275f2092af3ec26f42272daa4312c (diff) | |
| download | llvm-430a40d12eaa5a61792c4670955c110146902afb.zip llvm-430a40d12eaa5a61792c4670955c110146902afb.tar.gz llvm-430a40d12eaa5a61792c4670955c110146902afb.tar.bz2 | |
[NVPTX] extend type support for nvvm.{min,max,mulhi,sad} (#78385)
Ensure intrinsics and auto-upgrades support i16, i32, and i64 for for
`nvvm.{min,max,mulhi,sad}`
- `nvvm.min` and `nvvm.max`: These are auto-upgraded to `select`
instructions but it is still nice to support the 16 bit variants just in
case any generators of IR are still trying to use these intrinsics.
- `nvvm.sad` added both the 16 and 64 bit variants, also marked this
instruction as speculateble. These directly correspond to the PTX
`sad.{u16,s16,u64,s64}` instructions.
- `nvvm.mulhi` added the 16 bit variants. These directly correspond to
the PTX `mul.hi.{s,u}16` instructions.
Diffstat (limited to 'llvm/test/CodeGen/X86/apx')
0 files changed, 0 insertions, 0 deletions