diff options
author | Philip Reames <preames@rivosinc.com> | 2024-03-28 16:34:04 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-03-28 16:34:04 -0700 |
commit | 9ea0396f1608681e524e1159bfa8568f3ccfbb99 (patch) | |
tree | c0b159bde8a20d0036b6982cb9058292c24e07b9 /llvm/test/CodeGen/RISCV | |
parent | bbbcc1d99d08855069f4501c896c43a6d4d7b598 (diff) | |
download | llvm-9ea0396f1608681e524e1159bfa8568f3ccfbb99.zip llvm-9ea0396f1608681e524e1159bfa8568f3ccfbb99.tar.gz llvm-9ea0396f1608681e524e1159bfa8568f3ccfbb99.tar.bz2 |
[RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001)
I tried to add representative tests while not duplicating complete
coverage. If there's other tests you'd like to see, let me know.
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
-rw-r--r-- | llvm/test/CodeGen/RISCV/rv64zba.ll | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index d9d8363..c81c6ae 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -209,6 +209,24 @@ define i64 @sh1adduw_2(i64 %0, i64 %1) { ret i64 %5 } +define i64 @sh1adduw_3(i64 %0, i64 %1) { +; RV64I-LABEL: sh1adduw_3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 31 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: sh1adduw_3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh1add.uw a0, a0, a1 +; RV64ZBA-NEXT: ret + %3 = shl i64 %0, 1 + %4 = and i64 %3, 8589934590 + %5 = or disjoint i64 %4, %1 + ret i64 %5 +} + define signext i32 @sh2adduw(i32 signext %0, ptr %1) { ; RV64I-LABEL: sh2adduw: ; RV64I: # %bb.0: @@ -247,6 +265,24 @@ define i64 @sh2adduw_2(i64 %0, i64 %1) { ret i64 %5 } +define i64 @sh2adduw_3(i64 %0, i64 %1) { +; RV64I-LABEL: sh2adduw_3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 30 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: sh2adduw_3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 +; RV64ZBA-NEXT: ret + %3 = shl i64 %0, 2 + %4 = and i64 %3, 17179869180 + %5 = or disjoint i64 %4, %1 + ret i64 %5 +} + define i64 @sh3adduw(i32 signext %0, ptr %1) { ; RV64I-LABEL: sh3adduw: ; RV64I: # %bb.0: @@ -285,6 +321,24 @@ define i64 @sh3adduw_2(i64 %0, i64 %1) { ret i64 %5 } +define i64 @sh3adduw_3(i64 %0, i64 %1) { +; RV64I-LABEL: sh3adduw_3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 29 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: sh3adduw_3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh3add.uw a0, a0, a1 +; RV64ZBA-NEXT: ret + %3 = shl i64 %0, 3 + %4 = and i64 %3, 34359738360 + %5 = or disjoint i64 %4, %1 + ret i64 %5 +} + ; Type legalization inserts a sext_inreg after the first add. That add will be ; selected as sh2add which does not sign extend. SimplifyDemandedBits is unable ; to remove the sext_inreg because it has multiple uses. The ashr will use the @@ -335,6 +389,24 @@ define i64 @addmul6(i64 %a, i64 %b) { ret i64 %d } +define i64 @disjointormul6(i64 %a, i64 %b) { +; RV64I-LABEL: disjointormul6: +; RV64I: # %bb.0: +; RV64I-NEXT: li a2, 6 +; RV64I-NEXT: mul a0, a0, a2 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: disjointormul6: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh1add a0, a0, a0 +; RV64ZBA-NEXT: sh1add a0, a0, a1 +; RV64ZBA-NEXT: ret + %c = mul i64 %a, 6 + %d = or disjoint i64 %c, %b + ret i64 %d +} + define i64 @addmul10(i64 %a, i64 %b) { ; RV64I-LABEL: addmul10: ; RV64I: # %bb.0: @@ -1099,6 +1171,23 @@ define i64 @add4104(i64 %a) { ret i64 %c } +define i64 @add4104_2(i64 %a) { +; RV64I-LABEL: add4104_2: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a1, 1 +; RV64I-NEXT: addiw a1, a1, 8 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: add4104_2: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: li a1, 1026 +; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: ret + %c = or disjoint i64 %a, 4104 + ret i64 %c +} + define i64 @add8208(i64 %a) { ; RV64I-LABEL: add8208: ; RV64I: # %bb.0: |