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| author | Michael Maitland <michaeltmaitland@gmail.com> | 2024-03-26 20:17:22 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-26 20:17:22 -0400 |
| commit | 54a9f0e441c7cc3c954d24cfde00cb933306a9e9 (patch) | |
| tree | 34719e6c21b40cae3a7438cab9b6e2ab11687ea0 /llvm/test/CodeGen/RISCV | |
| parent | 3324f4d4f4bd82bc9fd43062d21a450671a3531b (diff) | |
| download | llvm-54a9f0e441c7cc3c954d24cfde00cb933306a9e9.zip llvm-54a9f0e441c7cc3c954d24cfde00cb933306a9e9.tar.gz llvm-54a9f0e441c7cc3c954d24cfde00cb933306a9e9.tar.bz2 | |
[RISCV][GISEL] Legalize, regbankselect, and instruction-select G_VSCALE (#85967)
G_VSCALE should be lowered using VLENB. If the type is not sXLen it
should be lowered using a G_VSCALE on the narrow type and a G_MUL.
regbank select and instruction select are straightforward so we really
only need to add tests to show it works.
Diffstat (limited to 'llvm/test/CodeGen/RISCV')
6 files changed, 850 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir new file mode 100644 index 0000000..27dfb3f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale32.mir @@ -0,0 +1,300 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test_1_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 3 + %0:gprb(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_2_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 2 + %0:gprb(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_3_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 3 + %3:gprb(s32) = G_LSHR %1, %2(s32) + %4:gprb(s32) = G_CONSTANT i32 3 + %0:gprb(s32) = G_MUL %3, %4 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_4_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 1 + %0:gprb(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_8_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_READ_VLENB + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_16_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 1 + %0:gprb(s32) = G_SHL %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_40_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40_s32 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:gprb(s32) = G_READ_VLENB + %2:gprb(s32) = G_CONSTANT i32 5 + %0:gprb(s32) = G_MUL %1, %2 + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_1_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 1 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_2_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 2 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_3_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 3 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_4_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 4 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 4 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_8_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 8 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_16_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 16 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 16 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... +--- +name: test_40_s64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40_s64 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 40 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:gprb(s32) = G_READ_VLENB + %18:gprb(s32) = G_CONSTANT i32 3 + %2:gprb(s32) = G_LSHR %17, %18(s32) + %15:gprb(s32) = G_CONSTANT i32 40 + %9:gprb(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir new file mode 100644 index 0000000..4a96be2 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vscale64.mir @@ -0,0 +1,139 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: test_1 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 3 + %2:gprb(s64) = G_LSHR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 2 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 2 + %2:gprb(s64) = G_LSHR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_3 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 3 + %2:gprb(s64) = G_LSHR %0, %1(s64) + %3:gprb(s64) = G_CONSTANT i64 3 + %4:gprb(s64) = G_MUL %2, %3 + $x10 = COPY %4(s64) + PseudoRET implicit $x10 + +... +--- +name: test_4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SRLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 1 + %2:gprb(s64) = G_LSHR %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_8 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... +--- +name: test_16 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1 + ; CHECK-NEXT: $x10 = COPY [[SLLI]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 1 + %2:gprb(s64) = G_SHL %0, %1(s64) + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: test_40 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40 + ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB + ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]] + ; CHECK-NEXT: $x10 = COPY [[MUL]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_READ_VLENB + %1:gprb(s64) = G_CONSTANT i64 5 + %2:gprb(s64) = G_MUL %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir new file mode 100644 index 0000000..899f795 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv32.mir @@ -0,0 +1,228 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_1_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_1_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 1 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_2_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_2_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 2 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_3_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_3_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 3 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_4_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_4_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 4 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_8_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_8_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 8 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_16_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_16_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 16 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_40_s32 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_40_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[READ_VLENB]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s32) = G_VSCALE i32 40 + $x10 = COPY %0 + PseudoRET implicit $x10 +... + +--- +name: test_1_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_1_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 1 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_2_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_2_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 2 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_3_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_3_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 3 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_4_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_4_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 4 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_8_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_8_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 8 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_16_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_16_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 16 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... +--- +name: test_40_s64 +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_40_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 40 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 40 + %1:_(s32) = G_TRUNC %0 + $x10 = COPY %1 + PseudoRET implicit $x10 +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir new file mode 100644 index 0000000..c0453a0 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-vscale-rv64.mir @@ -0,0 +1,110 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test_1 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_1 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 1 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_2 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_2 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 2 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_3 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_3 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 3 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_4 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_4 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 4 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_8 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_8 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: $x10 = COPY [[READ_VLENB]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 8 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_16 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_16 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 16 + $x10 = COPY %0 + PseudoRET implicit $x10 +... +--- +name: test_40 +body: | + bb.0.entry: + + ; CHECK-LABEL: name: test_40 + ; CHECK: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[READ_VLENB]], [[C]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = G_VSCALE i64 40 + $x10 = COPY %0 + PseudoRET implicit $x10 +... + + diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir new file mode 100644 index 0000000..ae3bb0a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv32.mir @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: test_s32 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_s32 + ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s32) = G_READ_VLENB + %2:_(s32) = G_CONSTANT i32 3 + %0:_(s32) = G_LSHR %1, %2(s32) + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... +--- +name: test_s64 +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_s64 + ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s32) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[READ_VLENB]], [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[LSHR]], [[C1]] + ; CHECK-NEXT: $x10 = COPY [[MUL]](s32) + ; CHECK-NEXT: PseudoRET implicit $x10 + %17:_(s32) = G_READ_VLENB + %18:_(s32) = G_CONSTANT i32 3 + %2:_(s32) = G_LSHR %17, %18(s32) + %15:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = G_MUL %2, %15 + $x10 = COPY %9(s32) + PseudoRET implicit $x10 + +... + diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir new file mode 100644 index 0000000..a7446d9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vscale-rv64.mir @@ -0,0 +1,25 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \ +# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \ +# RUN: -o - | FileCheck %s + +--- +name: test +legalized: true +tracksRegLiveness: true +body: | + bb.0.entry: + ; CHECK-LABEL: name: test + ; CHECK: [[READ_VLENB:%[0-9]+]]:gprb(s64) = G_READ_VLENB + ; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[READ_VLENB]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:_(s64) = G_READ_VLENB + %2:_(s64) = G_CONSTANT i64 3 + %0:_(s64) = G_LSHR %1, %2(s64) + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +... + |