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| author | Chen Zheng <czhengsz@cn.ibm.com> | 2024-04-03 04:45:40 -0400 |
|---|---|---|
| committer | Chen Zheng <czhengsz@cn.ibm.com> | 2024-04-03 04:46:29 -0400 |
| commit | 29c7d1a60c9d45e82f08cd7487178846ed5f9c6d (patch) | |
| tree | 513e3f49e4b5c99cd7b9418aafa7adc66fa272e8 /llvm/test/CodeGen/PowerPC | |
| parent | e5abd963c758bcfa1380d688bec31dddc834a2dd (diff) | |
| download | llvm-29c7d1a60c9d45e82f08cd7487178846ed5f9c6d.zip llvm-29c7d1a60c9d45e82f08cd7487178846ed5f9c6d.tar.gz llvm-29c7d1a60c9d45e82f08cd7487178846ed5f9c6d.tar.bz2 | |
[PPC] [NFC] add testcase for more store forwarding
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/legalize-vaarg.ll | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll index b7f8b8a..8980049 100644 --- a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll +++ b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE ;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE +;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -ppc-gather-alias-max-depth=0 | FileCheck %s -check-prefix=FORWARD define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) { ; BE-LABEL: test_large_vec_vaarg: @@ -35,6 +36,22 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) { ; LE-NEXT: lxvd2x 0, 0, 3 ; LE-NEXT: xxswapd 35, 0 ; LE-NEXT: blr +; +; FORWARD-LABEL: test_large_vec_vaarg: +; FORWARD: # %bb.0: +; FORWARD-NEXT: ld 3, -8(1) +; FORWARD-NEXT: addi 3, 3, 15 +; FORWARD-NEXT: rldicr 3, 3, 0, 59 +; FORWARD-NEXT: addi 4, 3, 16 +; FORWARD-NEXT: std 4, -8(1) +; FORWARD-NEXT: ld 4, -8(1) +; FORWARD-NEXT: lvx 2, 0, 3 +; FORWARD-NEXT: addi 4, 4, 15 +; FORWARD-NEXT: rldicr 3, 4, 0, 59 +; FORWARD-NEXT: addi 4, 3, 16 +; FORWARD-NEXT: std 4, -8(1) +; FORWARD-NEXT: lvx 3, 0, 3 +; FORWARD-NEXT: blr %args = alloca ptr, align 4 %x = va_arg ptr %args, <8 x i32> ret <8 x i32> %x |