diff options
| author | Vitaly Buka <vitalybuka@google.com> | 2024-01-17 21:07:59 -0800 |
|---|---|---|
| committer | Vitaly Buka <vitalybuka@google.com> | 2024-01-17 21:07:59 -0800 |
| commit | 2867978488b65ffeb32f77e098b5c61b1c611727 (patch) | |
| tree | 340262ad8444a008531362c161c7aec3e8077d9b /llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll | |
| parent | 430a40d12eaa5a61792c4670955c110146902afb (diff) | |
| parent | f6617091a982c0802e9b980f2ce7e11a1355c38b (diff) | |
| download | llvm-users/vitalybuka/spr/main.sanitizer-skip-includec-from-summary.zip llvm-users/vitalybuka/spr/main.sanitizer-skip-includec-from-summary.tar.gz llvm-users/vitalybuka/spr/main.sanitizer-skip-includec-from-summary.tar.bz2 | |
[𝘀𝗽𝗿] changes introduced through rebaseusers/vitalybuka/spr/main.sanitizer-skip-includec-from-summary
Created using spr 1.3.4
[skip ci]
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll index a2b7e9d..05186ac 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll @@ -1433,6 +1433,72 @@ define amdgpu_kernel void @test_setreg_set_4_bits_straddles_round_and_denorm() { ret void } +define amdgpu_ps void @test_63489(i32 inreg %var.mode) { +; GFX6-LABEL: test_63489: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9] +; GFX6-NEXT: ;;#ASMSTART +; GFX6-NEXT: ;;#ASMEND +; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] +; +; GFX789-LABEL: test_63489: +; GFX789: ; %bb.0: +; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9] +; GFX789-NEXT: ;;#ASMSTART +; GFX789-NEXT: ;;#ASMEND +; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] +; +; GFX10-LABEL: test_63489: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9] +; GFX10-NEXT: ;;#ASMSTART +; GFX10-NEXT: ;;#ASMEND +; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] +; +; GFX11-LABEL: test_63489: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9] +; GFX11-NEXT: ;;#ASMSTART +; GFX11-NEXT: ;;#ASMEND +; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] + call void @llvm.amdgcn.s.setreg(i32 63489, i32 %var.mode) + call void asm sideeffect "", ""() + ret void +} + +define amdgpu_ps void @test_minus_2047(i32 inreg %var.mode) { +; GFX6-LABEL: test_minus_2047: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9] +; GFX6-NEXT: ;;#ASMSTART +; GFX6-NEXT: ;;#ASMEND +; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] +; +; GFX789-LABEL: test_minus_2047: +; GFX789: ; %bb.0: +; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9] +; GFX789-NEXT: ;;#ASMSTART +; GFX789-NEXT: ;;#ASMEND +; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] +; +; GFX10-LABEL: test_minus_2047: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9] +; GFX10-NEXT: ;;#ASMSTART +; GFX10-NEXT: ;;#ASMEND +; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] +; +; GFX11-LABEL: test_minus_2047: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9] +; GFX11-NEXT: ;;#ASMSTART +; GFX11-NEXT: ;;#ASMEND +; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] + call void @llvm.amdgcn.s.setreg(i32 -2047, i32 %var.mode) + call void asm sideeffect "", ""() + ret void +} + ; FIXME: Broken for DAG ; define void @test_setreg_roundingmode_var_vgpr(i32 %var.mode) { ; call void @llvm.amdgcn.s.setreg(i32 4097, i32 %var.mode) |