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| author | Nick Desaulniers <nickdesaulniers@users.noreply.github.com> | 2023-09-13 13:31:24 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-13 13:31:24 -0700 |
| commit | 86735a4353aee4a3ba1e2feea173a7cc659c7a60 (patch) | |
| tree | 935e992ad4a313bf0c1e683ed6f12a5fe391590f /llvm/lib/Target/XCore | |
| parent | 008bd84625db6a56970ac944cc29944f0321809b (diff) | |
| download | llvm-86735a4353aee4a3ba1e2feea173a7cc659c7a60.zip llvm-86735a4353aee4a3ba1e2feea173a7cc659c7a60.tar.gz llvm-86735a4353aee4a3ba1e2feea173a7cc659c7a60.tar.bz2 | |
reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66264)
reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003)
This reverts commit ee643b706be2b6bef9980b25cc9cc988dab94bb5.
Fix up build failures in targets I missed in #66003
Kept as 3 commits for reviewers to see better what's changed. Will
squash when
merging.
- reland [InlineAsm] wrap ConstraintCode in enum class NFC (#66003)
- fix all the targets I missed in #66003
- fix off by one found by llvm/test/CodeGen/SystemZ/inline-asm-addr.ll
Diffstat (limited to 'llvm/lib/Target/XCore')
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 949b88a..54ee759 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -71,7 +71,8 @@ namespace { // Complex Pattern Selectors. bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, std::vector<SDValue> &OutOps) override; // Include the pieces autogenerated from the target description. @@ -114,13 +115,13 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, return false; } -bool XCoreDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, - std::vector<SDValue> &OutOps) { +bool XCoreDAGToDAGISel::SelectInlineAsmMemoryOperand( + const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, + std::vector<SDValue> &OutOps) { SDValue Reg; switch (ConstraintID) { default: return true; - case InlineAsm::Constraint_m: // Memory. + case InlineAsm::ConstraintCode::m: // Memory. switch (Op.getOpcode()) { default: return true; case XCoreISD::CPRelativeWrapper: |